Paul Mathieu
36bc1417b6
cpu: more instruction pipelining
...
This is needed to make WNS room for fetching instructions from SRAM.
2021-04-17 23:02:58 -07:00
Paul Mathieu
6825ce464f
cc: fix load bug
2021-03-20 21:49:40 -07:00
Paul Mathieu
a4005ade77
dsp: small refactor
2021-03-20 21:27:36 -07:00
Paul Mathieu
ef81ec3b12
cc: mostly fixed function calls
2021-03-20 21:27:26 -07:00
Paul Mathieu
eb303641d9
cc: fix typo
2021-03-20 21:25:01 -07:00
Paul Mathieu
f7b7118278
dsp: non-functional code. needs funcall refactor in cc
2021-03-18 20:14:00 -07:00
Paul Mathieu
b70cdd13c4
Add partial support for 8-bit loads
...
We're big-endian.
when we have this in memory:
00 01 02 03
And we need the first byte, we load the first 16-bit word:
0x0001
The first byte is then in the upper part of the word, and requires
a right shift by 8.
So any load into an 8-bit typed container needs to shift stuff.
So far, stores from/to the stack are exempted, they always load/store
full 16-bit words.
And a few othe rminor things. Like string null terminators.
And escaped characters in character literals.
Can you believe it's spelled 'literal', with a single t?
Me neither.
2021-03-18 08:35:23 -07:00
Paul Mathieu
5612f23181
dsp: flash these LEDs
2021-03-14 18:09:05 -07:00
Paul Mathieu
38542f4431
dsp: add make target for bitstream
2021-03-14 18:08:53 -07:00
Paul Mathieu
7ba6746ddd
cpu: streamline hold a little
2021-03-14 18:08:13 -07:00
Paul Mathieu
48ffd4eb6d
cc: fix field access bug
2021-03-14 18:07:52 -07:00
Paul Mathieu
0a38fdb9fd
gitignore: a few more things
2021-03-14 12:18:36 -07:00
Paul Mathieu
6ea04f1f6b
dsp: some UART logging \o/
2021-03-14 12:18:01 -07:00
Paul Mathieu
6609dfa4b1
uart: can now write more stuff
2021-03-14 12:17:48 -07:00
Paul Mathieu
7841987b6e
cc: add support for string literals and some stuff
...
- string literals added as rodata
- fixed register shuffling in for/while loops & fun calls
- a few other fixes
2021-03-14 12:16:21 -07:00
Paul Mathieu
54c69dd962
dsp: add missing alu.vhdl in makefile
2021-03-14 12:14:55 -07:00
Paul Mathieu
d1d0e421ce
cpu: make BEQ and BNEQ only PC-relative
2021-03-14 12:14:29 -07:00
Paul Mathieu
24c6831813
Small fixes for synthesis
2021-03-13 21:02:54 -08:00
Paul Mathieu
14dba00fd0
Add dsp
...
With:
- LED control
- UART
- PDM out
- square wave generator (DMA to PDM out (was it really necessary?))
- sample program that plays a square wave from UART values
2021-03-13 15:50:25 -08:00
Paul Mathieu
75b5488b8d
uart: upgrade C api
2021-03-13 15:49:28 -08:00
Paul Mathieu
5d5eeb45cc
sysbus: fix reading not holding address
2021-03-13 15:49:00 -08:00
Paul Mathieu
960c8956b2
wave: add header
2021-03-13 15:47:24 -08:00
Paul Mathieu
963cd1059e
square: stay quiet if period = 0
2021-03-13 15:46:20 -08:00
Paul Mathieu
790c08f1f2
ld: now generates a full rom vhdl from template
2021-03-13 15:44:48 -08:00
Paul Mathieu
e1557ad4b6
cc: add -I preprocessor option
2021-03-13 15:44:22 -08:00
Paul Mathieu
a3a67105eb
cc: add support for structs
...
- now we keep track of expression type
- added '|' and '|=' operators
- implemented '->' operator
- minor cleanups
2021-03-13 15:42:39 -08:00
Paul Mathieu
3b56750a73
hello: simplify interconnect
2021-03-12 14:18:37 -08:00
Paul Mathieu
50dedf1dd8
wave: add square waveform generator
2021-03-08 18:58:52 -08:00
Paul Mathieu
c6eaf0e9e6
gitignore: a few more things
2021-03-06 19:12:08 -08:00
Paul Mathieu
1e6dc25c88
cpu: wait when mem_busy is high
2021-03-06 19:11:11 -08:00
Paul Mathieu
634596fd0f
Exctract cpu into its own module
2021-03-06 16:37:42 -08:00
Paul Mathieu
9e61fd9456
Add multi master sys bus
2021-03-06 16:36:57 -08:00
Paul Mathieu
ea52764fc4
Add pdmout module
2021-02-28 22:11:17 -08:00
Paul Mathieu
2f210dd561
uart: add ledctrl app
2021-02-22 20:37:18 -08:00
Paul Mathieu
b8ee42bfc2
Add .gitignore
2021-02-22 20:36:47 -08:00
Paul Mathieu
44a3a03147
Fix relocs
2021-02-22 20:35:09 -08:00
Paul Mathieu
edf167ff2b
Fix initial stack pointer
2021-02-22 20:34:54 -08:00
Paul Mathieu
f8586a3fb0
Fix eq
2021-02-22 20:34:35 -08:00
Paul Mathieu
fbeb22df5a
Implement post_decrement
2021-02-22 20:34:17 -08:00
Paul Mathieu
abfd8d3647
Fix shl
2021-02-22 20:33:58 -08:00
Paul Mathieu
f3928f52a4
Fix if-else regs
2021-02-22 20:33:35 -08:00
Paul Mathieu
64d440c94b
Word-precise imm for BEQ and BNEQ
2021-02-22 20:33:05 -08:00
Paul Mathieu
f59b3efb9f
Fix a few details
2021-02-18 21:27:20 -08:00
Paul Mathieu
0157e235e4
Add support for char litterals and <<
...
Also streamline cc.py to do it all:
- cpp
- cc
- as
LD is still a separate step
2021-02-18 21:20:35 -08:00
Paul Mathieu
0b77dc5d20
Add base submodule
2021-02-17 13:23:18 -08:00
Paul Mathieu
6446ed86f1
Ad reset conditioner
2021-02-17 13:22:23 -08:00
Paul Mathieu
363944d417
Initial commit
2021-02-17 13:20:30 -08:00
