Ad reset conditioner

This commit is contained in:
Paul Mathieu 2021-02-17 13:22:23 -08:00
parent 363944d417
commit 6446ed86f1

31
first/reset_conditioner.v Normal file
View File

@ -0,0 +1,31 @@
/*
Parameters:
STAGES = 4
*/
module reset_conditioner (
input clk,
input rin,
output reg rout
);
localparam STAGES = 3'h4;
reg [3:0] M_stage_d, M_stage_q = 4'hf;
always @* begin
M_stage_d = M_stage_q;
M_stage_d = {M_stage_q[0+2-:3], 1'h0};
rout = M_stage_q[3+0-:1];
end
always @(posedge clk) begin
if (rin == 1'b1) begin
M_stage_q <= 4'hf;
end else begin
M_stage_q <= M_stage_d;
end
end
endmodule