Paul Mathieu 38542f4431 dsp: add make target for bitstream

2021-03-14 18:08:53 -07:00

base @ e27480fa5d

Add base submodule

2021-02-17 13:23:18 -08:00

cpu

cpu: streamline hold a little

2021-03-14 18:08:13 -07:00

dsp

dsp: add make target for bitstream

2021-03-14 18:08:53 -07:00

first

hello: simplify interconnect

2021-03-12 14:18:37 -08:00

sysbus

Small fixes for synthesis

2021-03-13 21:02:54 -08:00

tools

cc: fix field access bug

2021-03-14 18:07:52 -07:00

uart

uart: can now write more stuff

2021-03-14 12:17:48 -07:00

wave

wave: add header

2021-03-13 15:47:24 -08:00

.gitignore

gitignore: a few more things

2021-03-14 12:18:36 -07:00

.gitmodules

Add base submodule

2021-02-17 13:23:18 -08:00

Description

No description provided

2 MiB

Languages

C 69.2%

C++ 15.4%

VHDL 8.1%

Python 5.2%

Tcl 1%

Other 0.8%