Go to file
2021-03-13 15:46:20 -08:00
base@e27480fa5d Add base submodule 2021-02-17 13:23:18 -08:00
cpu cpu: wait when mem_busy is high 2021-03-06 19:11:11 -08:00
first hello: simplify interconnect 2021-03-12 14:18:37 -08:00
sysbus Add multi master sys bus 2021-03-06 16:36:57 -08:00
tools ld: now generates a full rom vhdl from template 2021-03-13 15:44:48 -08:00
uart uart: add ledctrl app 2021-02-22 20:37:18 -08:00
wave square: stay quiet if period = 0 2021-03-13 15:46:20 -08:00
.gitignore gitignore: a few more things 2021-03-06 19:12:08 -08:00
.gitmodules Add base submodule 2021-02-17 13:23:18 -08:00