Paul Mathieu 6ea04f1f6b dsp: some UART logging \o/

2021-03-14 12:18:01 -07:00

base @ e27480fa5d

Add base submodule

2021-02-17 13:23:18 -08:00

cpu

cpu: make BEQ and BNEQ only PC-relative

2021-03-14 12:14:29 -07:00

dsp

dsp: some UART logging \o/

2021-03-14 12:18:01 -07:00

first

hello: simplify interconnect

2021-03-12 14:18:37 -08:00

sysbus

Small fixes for synthesis

2021-03-13 21:02:54 -08:00

tools

cc: add support for string literals and some stuff

2021-03-14 12:16:21 -07:00

uart

uart: can now write more stuff

2021-03-14 12:17:48 -07:00

wave

wave: add header

2021-03-13 15:47:24 -08:00

.gitignore

gitignore: a few more things

2021-03-06 19:12:08 -08:00

.gitmodules

Add base submodule

2021-02-17 13:23:18 -08:00

Description

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2 MiB

Languages

C 69.2%

C++ 15.4%

VHDL 8.1%

Python 5.2%

Tcl 1%

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