dsp: add make target for bitstream
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7ba6746ddd
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@ -1,6 +1,7 @@
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all: sim rom
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all: sim rom
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sim: dsp_test.ghw
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sim: dsp_test.ghw
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rom: boot_rom.gen.vhdl
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rom: boot_rom.gen.vhdl
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bin: ../lab/dsp/au_base_project.runs/impl_1/au_top.bin
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CC = ../bin/cc
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CC = ../bin/cc
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LD = ../bin/ld
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LD = ../bin/ld
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@ -17,6 +18,12 @@ sources = boot_rom.gen.vhdl dsp.vhdl \
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../uart/uart.vhdl \
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../uart/uart.vhdl \
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../first/ram.vhdl
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../first/ram.vhdl
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../lab/dsp/au_base_project.runs/impl_1/au_top.bin: ../lab/dsp/au_base_project.runs/synth_1/au_top.dcp
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../lab/dsp/au_base_project.runs/impl_1/runme.sh
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../lab/dsp/au_base_project.runs/synth_1/au_top.dcp: $(sources)
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../lab/dsp/au_base_project.runs/synth_1/runme.sh
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%.gen.vhdl:
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%.gen.vhdl:
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$(LD) -o $@ --vhdl $*.vhdl.in $^
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$(LD) -o $@ --vhdl $*.vhdl.in $^
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@ -29,7 +36,7 @@ sources = boot_rom.gen.vhdl dsp.vhdl \
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work-obj93.cf: $(sim_sources) $(sources)
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work-obj93.cf: $(sim_sources) $(sources)
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ghdl -a $^
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ghdl -a $^
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PHONY: sim clean
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PHONY: bin sim rom clean
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clean:
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clean:
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rm -rf *.o *.gen.vhdl *.ghw work-obj93.cf
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rm -rf *.o *.gen.vhdl *.ghw work-obj93.cf
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