From 38542f4431e45aecd4d41021de28ba5b5360f43f Mon Sep 17 00:00:00 2001
From: Paul Mathieu <paulmathieu@google.com>
Date: Sun, 14 Mar 2021 18:08:53 -0700
Subject: [PATCH] dsp: add make target for bitstream

---
 dsp/makefile | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/dsp/makefile b/dsp/makefile
index b3fb480..da9c20d 100644
--- a/dsp/makefile
+++ b/dsp/makefile
@@ -1,6 +1,7 @@
 all: sim rom
 sim: dsp_test.ghw
 rom: boot_rom.gen.vhdl
+bin: ../lab/dsp/au_base_project.runs/impl_1/au_top.bin
 
 CC = ../bin/cc
 LD = ../bin/ld
@@ -17,6 +18,12 @@ sources = boot_rom.gen.vhdl dsp.vhdl      \
 	  ../uart/uart.vhdl               \
 	  ../first/ram.vhdl
 
+../lab/dsp/au_base_project.runs/impl_1/au_top.bin: ../lab/dsp/au_base_project.runs/synth_1/au_top.dcp
+	../lab/dsp/au_base_project.runs/impl_1/runme.sh
+
+../lab/dsp/au_base_project.runs/synth_1/au_top.dcp: $(sources)
+	../lab/dsp/au_base_project.runs/synth_1/runme.sh
+
 
 %.gen.vhdl:
 	$(LD) -o $@ --vhdl $*.vhdl.in $^
@@ -29,7 +36,7 @@ sources = boot_rom.gen.vhdl dsp.vhdl      \
 work-obj93.cf: $(sim_sources) $(sources)
 	ghdl -a $^
 
-PHONY: sim clean
+PHONY: bin sim rom clean
 
 clean:
 	rm -rf *.o *.gen.vhdl *.ghw work-obj93.cf