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square: stay quiet if period = 0

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This commit is contained in:
Paul Mathieu 2021-03-13 15:46:20 -08:00
parent 790c08f1f2
commit 963cd1059e
1 changed files with 14 additions and 7 deletions
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21
wave/square.vhdl
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@ -38,21 +38,28 @@ architecture Behavioral of square is
signal enabled: std_logic; signal enabled: std_logic;
signal counter: unsigned(23 downto 0); signal counter: unsigned(23 downto 0);
signal active: std_logic;
begin begin
-- counter process -- counter process
-- drives counter -- drives counter, active
process(clk, rst) process(clk, rst)
begin begin
if rst = '1' then if rst = '1' then
counter <= to_unsigned(0, 24); counter <= to_unsigned(0, 24);
active <= '0';
elsif rising_edge(clk) then elsif rising_edge(clk) then
if enabled = '0' or counter(22 downto 7) = unsigned(period) then active <= '0';
counter <= to_unsigned(0, 24); counter <= to_unsigned(0, 24);
else
counter <= counter + 1; if enabled = '1' and unsigned(period) /= 0 then
if counter(22 downto 7) = unsigned(period) then
active <= '1';
else
counter <= counter + 1;
end if;
end if; end if;
end if; end if;
@ -76,9 +83,9 @@ begin
m_we <= '0'; m_we <= '0';
if enabled = '1' then if enabled = '1' then
if counter = 0 and m_busy = '1' then if active = '1' and m_busy = '1' then
deferred := '1'; deferred := '1';
elsif deferred = '1' or (counter = 0 and m_busy = '0') then elsif deferred = '1' or (active = '1' and m_busy = '0') then
m_we <= '1'; m_we <= '1';
m_addr <= out_addr; m_addr <= out_addr;
if high = '1' then if high = '1' then