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Small fixes for synthesis

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Paul Mathieu 2021-03-13 21:02:54 -08:00
parent 14dba00fd0
commit 24c6831813
3 changed files with 5 additions and 2 deletions
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2
cpu/cpu.vhdl
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@ -80,7 +80,7 @@ begin
code_addr <= reg_q(14); code_addr <= reg_q(14);
process(code_data, reg_q, mem_in, mem_busy, alu_q, alu_flag, cpu_state, load_addr, load_reg) is process(code_data, reg_q, mem_in, mem_busy, alu_q, alu_flag, cpu_state, load_addr, load_reg, hold_inst) is
variable inst: std_logic_vector(15 downto 0); variable inst: std_logic_vector(15 downto 0);
variable regn_0: natural; variable regn_0: natural;
variable regn_1: natural; variable regn_1: natural;

2
dsp/dsp.vhdl
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@ -232,7 +232,7 @@ begin
end if; end if;
end process; end process;
process(bus_addr, bus_mosi, bus_write, mem_out, rst, rom_data_out, led_r, bus_read) process(bus_addr, bus_mosi, bus_write, mem_out, rst, rom_data_out, led_r, bus_read, uart_dout)
begin begin
bus_miso <= x"0000"; bus_miso <= x"0000";

3
sysbus/sysbus.vhdl
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@ -58,7 +58,10 @@ begin
end if; end if;
pend_next <= pend; pend_next <= pend;
pend_addr_next <= pend_addr;
pend_wdata_next <= pend_wdata;
owner_next <= "00"; owner_next <= "00";
state_next <= IDLE;
bus_we <= '0'; bus_we <= '0';
bus_re <= '0'; bus_re <= '0';