219 lines
7.0 KiB
VHDL
219 lines
7.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity cpu is
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port(
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clk: in std_logic;
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rst: in std_logic;
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code_data: in std_logic_vector(15 downto 0);
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code_addr: out std_logic_vector(15 downto 0);
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mem_in: in std_logic_vector(15 downto 0);
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mem_out: out std_logic_vector(15 downto 0);
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mem_addr: out std_logic_vector(15 downto 0);
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mem_write: out std_logic;
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mem_read: out std_logic;
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mem_busy: in std_logic
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);
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end entity cpu;
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architecture behavior of cpu is
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component alu is
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port(
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a: in std_logic_vector(15 downto 0);
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b: in std_logic_vector(15 downto 0);
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sel: in std_logic_vector(3 downto 0);
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flag: out std_logic;
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q: out std_logic_vector(15 downto 0)
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);
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end component;
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component reg is
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port(
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clk : in std_logic;
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rst : in std_logic;
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d : in std_logic_vector(15 downto 0);
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q : out std_logic_vector(15 downto 0)
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);
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end component;
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signal alu_a: std_logic_vector(15 downto 0);
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signal alu_b: std_logic_vector(15 downto 0);
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signal alu_q: std_logic_vector(15 downto 0);
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signal alu_sel: std_logic_vector(3 downto 0);
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signal alu_flag: std_logic;
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signal load_reg_next, load_reg: std_logic_vector(15 downto 0);
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signal load_addr_next, load_addr: std_logic_vector(15 downto 0);
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signal hold_inst_next, hold_inst: std_logic_vector(15 downto 0);
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type regbank is array(0 to 15) of std_logic_vector(15 downto 0);
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signal reg_d: regbank;
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signal reg_q: regbank;
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type cpu_state_t is (RUN, LOAD, BRANCH, WAIT_MEM);
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signal cpu_state, cpu_state_next: cpu_state_t;
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begin
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cpu_alu: alu port map(a => alu_a, b => alu_b, sel => alu_sel, flag => alu_flag, q => alu_q);
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load_reg_r: reg port map(clk => clk, rst => rst, d => load_reg_next, q => load_reg);
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load_addr_r: reg port map(clk => clk, rst => rst, d => load_addr_next, q => load_addr);
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hold_inst_r: reg port map(clk => clk, rst => rst, d => hold_inst_next, q => hold_inst);
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allregs:
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for i in 0 to 15 generate
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regx: reg port map(clk => clk, rst => rst, d => reg_d(i), q => reg_q(i));
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end generate allregs;
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process(clk, rst)
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begin
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if rst = '1' then
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cpu_state <= BRANCH; -- wait a cycle at first
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elsif rising_edge(clk) then
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cpu_state <= cpu_state_next;
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end if;
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end process;
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code_addr <= reg_q(14);
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process(code_data, reg_q, mem_in, mem_busy, alu_q, alu_flag, cpu_state, load_addr, load_reg, hold_inst) is
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variable inst: std_logic_vector(15 downto 0);
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variable regn_0: natural;
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variable regn_1: natural;
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variable regn_2: natural;
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variable do_alu: std_logic;
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begin
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mem_write <= '0';
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mem_read <= '0';
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mem_addr <= x"0000";
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mem_out <= x"0000";
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alu_sel <= "0000";
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alu_a <= x"0000";
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alu_b <= x"0000";
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do_alu := '0';
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for i in 0 to 15 loop
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reg_d(i) <= reg_q(i);
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end loop;
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cpu_state_next <= RUN;
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load_reg_next <= load_reg;
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load_addr_next <= load_addr;
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hold_inst_next <= hold_inst;
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case cpu_state is
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when RUN =>
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reg_d(14) <= std_logic_vector(unsigned(reg_q(14)) + 2);
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inst := code_data;
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when LOAD =>
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inst := x"0000"; -- NOP
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mem_addr <= load_addr; -- maintain this until we're done reading
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if load_reg(3 downto 0) = x"e" then
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cpu_state_next <= BRANCH;
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else
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reg_d(14) <= std_logic_vector(unsigned(reg_q(14)) + 2);
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end if;
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regn_0 := to_integer(unsigned(load_reg(3 downto 0)));
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reg_d(regn_0) <= mem_in;
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when BRANCH =>
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inst := x"0000"; -- NOP
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reg_d(14) <= std_logic_vector(unsigned(reg_q(14)) + 2);
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when WAIT_MEM =>
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cpu_state_next <= RUN;
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inst := hold_inst;
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reg_d(14) <= std_logic_vector(unsigned(reg_q(14)) + 2);
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end case;
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regn_0 := to_integer(unsigned(inst(11 downto 8)));
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regn_1 := to_integer(unsigned(inst(7 downto 4)));
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regn_2 := to_integer(unsigned(inst(3 downto 0)));
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case inst(15 downto 12) is
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when "0000" => -- NOP
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when "0001" => -- LOAD rn, [rm, imm] (imm is signed 4 bits)
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if mem_busy = '1' then
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reg_d(14) <= reg_q(14); -- halt the prefetcher
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hold_inst_next <= inst;
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cpu_state_next <= WAIT_MEM;
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else
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mem_read <= '1';
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cpu_state_next <= LOAD;
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reg_d(14) <= reg_q(14); -- halt the prefetcher
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load_addr_next <= std_logic_vector(signed(reg_q(regn_1)) + signed(inst(3 downto 0) & '0'));
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mem_addr <= std_logic_vector(signed(reg_q(regn_1)) + signed(inst(3 downto 0) & '0'));
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load_reg_next(3 downto 0) <= inst(11 downto 8);
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end if;
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when "0010" => -- STORE rn, [rm, imm]
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if mem_busy = '1' then
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reg_d(14) <= reg_q(14); -- halt the prefetcher
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hold_inst_next <= inst;
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cpu_state_next <= WAIT_MEM;
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else
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mem_write <= '1';
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mem_addr <= std_logic_vector(signed(reg_q(regn_1)) + signed(inst(3 downto 0) & '0'));
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mem_out <= reg_q(regn_0);
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end if;
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--- ALU stuff
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when "0011" => do_alu := '1'; -- ADD rd, rn, rm (rd := rn + rm)
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when "0100" => do_alu := '1'; -- SUB rd, rn, rm (rd := rn - rm)
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when "0101" => do_alu := '1'; -- OR rd, rn, rm (rd := rn or rm)
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when "0110" => do_alu := '1'; -- AND rd, rn, rm (rd := rn and rm)
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when "0111" => do_alu := '1'; -- NOT rd, rn (rd := not rn)
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when "1000" => do_alu := '1'; -- XOR rd, rn, rm (rd := rn xor rm)
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when "1001" => -- SETH rd, imm
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reg_d(regn_0)(15 downto 8) <= inst(7 downto 0);
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when "1010" => -- SHR rd, rn, imm (rd := rn >> imm)
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alu_sel <= inst(15 downto 12);
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alu_a <= reg_q(regn_1);
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alu_b <= x"000" & inst(3 downto 0);
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reg_d(regn_0) <= alu_q;
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when "1011" => do_alu := '1'; -- MUL rd, rn, rm (rd := rn * rm)
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when "1100" => -- CMP rn, rm (flag := 1 if equal)
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alu_sel <= "1100";
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alu_a <= reg_q(regn_0);
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alu_b <= reg_q(regn_1);
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reg_d(15)(0) <= alu_flag;
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when "1101" => -- BEQ [rn, imm] (jump to [rn, imm] if flag is set, imm is signed 8 bits)
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if reg_q(15)(0) = '1' then
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reg_d(14) <= std_logic_vector(signed(reg_q(regn_0)) + signed(inst(7 downto 0) & '0'));
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cpu_state_next <= BRANCH;
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end if;
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when "1110" => -- SET rd, imm (rd := imm, imm is 8 bit)
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reg_d(regn_0) <= x"00" & inst(7 downto 0);
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when "1111" => -- BNEQ [rn, imm]
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if reg_q(15)(0) = '0' then
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reg_d(14) <= std_logic_vector(signed(reg_q(regn_0)) + signed(inst(7 downto 0) & '0'));
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cpu_state_next <= BRANCH;
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end if;
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when others => -- do nothing
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end case;
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if do_alu = '1' then
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-- 1:1 mapping
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alu_sel <= inst(15 downto 12);
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alu_a <= reg_q(regn_1);
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alu_b <= reg_q(regn_2);
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reg_d(regn_0) <= alu_q;
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reg_d(15)(0) <= alu_flag;
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if inst(11 downto 8) = x"e" then
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cpu_state_next <= BRANCH;
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end if;
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end if;
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end process;
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end behavior;
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