Small fixes for synthesis

2021-03-13 21:02:54 -08:00
parent 14dba00fd0
commit 24c6831813
3 changed files with 5 additions and 2 deletions
--- a/cpu/cpu.vhdl
+++ b/cpu/cpu.vhdl
@@ -80,7 +80,7 @@ begin

  code_addr <= reg_q(14);

-  process(code_data, reg_q, mem_in, mem_busy, alu_q, alu_flag, cpu_state, load_addr, load_reg) is
+  process(code_data, reg_q, mem_in, mem_busy, alu_q, alu_flag, cpu_state, load_addr, load_reg, hold_inst) is
    variable inst: std_logic_vector(15 downto 0);
    variable regn_0: natural;
    variable regn_1: natural;