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uart: fix synthesis warnings

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This commit is contained in:
Paul Mathieu 2021-04-17 23:07:56 -07:00
parent 0e6a311610
commit 102e9cbd07
1 changed files with 55 additions and 50 deletions
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105
uart/uart.vhdl
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@ -32,7 +32,7 @@ end uart;
-- Mnemonic: receive from the left, transmit to the right -- Mnemonic: receive from the left, transmit to the right
architecture Behavioral of uart is architecture Behavioral of uart is
constant BAUD: positive := 115_200; constant BAUD: positive := 1_000_000;
constant SYSFREQ: natural := 100_000_000; constant SYSFREQ: natural := 100_000_000;
constant CLKCNT: natural := SYSFREQ / BAUD; constant CLKCNT: natural := SYSFREQ / BAUD;
@ -78,32 +78,34 @@ begin
for i in 0 to 3 loop for i in 0 to 3 loop
rxfifo(i) <= x"00"; rxfifo(i) <= x"00";
end loop; end loop;
elsif rising_edge(clk) and uarten = '1' then elsif rising_edge(clk) then
rxpushed <= '0'; if uarten = '1' then
rxpushed <= '0';
case rxstate is case rxstate is
when IDLE => when IDLE =>
if rx_pin = '0' then -- start bit!! (hopefully) if rx_pin = '0' then -- start bit!! (hopefully)
rxshift <= x"00"; rxshift <= x"00";
rxshiftcnt <= "0000"; rxshiftcnt <= "0000";
rxstate <= SHIFT_IN; rxstate <= SHIFT_IN;
end if;
when SHIFT_IN =>
if rxshiftcnt = 8 then
-- by now we should be seeing the stop bit, check
if rx_pin = '1' then -- all good, push away
for i in 2 downto 0 loop -- right to left
rxfifo(i + 1) <= rxfifo(i);
end loop;
rxfifo(0) <= rxshift;
rxpushed <= '1';
end if; end if;
rxstate <= IDLE; -- either way, we're done when SHIFT_IN =>
else if rxshiftcnt = 8 then
rxshift <= rx_pin & rxshift(7 downto 1); -- by now we should be seeing the stop bit, check
rxshiftcnt <= rxshiftcnt + 1; if rx_pin = '1' then -- all good, push away
end if; for i in 2 downto 0 loop -- right to left
end case; rxfifo(i + 1) <= rxfifo(i);
end loop;
rxfifo(0) <= rxshift;
rxpushed <= '1';
end if;
rxstate <= IDLE; -- either way, we're done
else
rxshift <= rx_pin & rxshift(7 downto 1);
rxshiftcnt <= rxshiftcnt + 1;
end if;
end case;
end if;
end if; end if;
end process; end process;
@ -117,30 +119,32 @@ begin
txshift <= x"00"; txshift <= x"00";
txshiftcnt <= "0000"; txshiftcnt <= "0000";
tx_pin <= '1'; tx_pin <= '1';
elsif rising_edge(clk) and uarten = '1' then elsif rising_edge(clk) then
txpopped <= '0'; if uarten = '1' then
txpopped <= '0';
case txstate is case txstate is
when IDLE => when IDLE =>
if txcnt > 0 then if txcnt > 0 then
txshiftcnt <= "0000"; txshiftcnt <= "0000";
tx_pin <= '0'; -- start bit tx_pin <= '0'; -- start bit
txstate <= SHIFT_OUT; txstate <= SHIFT_OUT;
txshift <= txfifo(0); txshift <= txfifo(0);
txpopped <= '1'; txpopped <= '1';
else else
tx_pin <= '1'; tx_pin <= '1';
end if; end if;
when SHIFT_OUT => when SHIFT_OUT =>
if txshiftcnt = 8 then if txshiftcnt = 8 then
tx_pin <= '1'; tx_pin <= '1';
txstate <= IDLE; txstate <= IDLE;
else else
txshiftcnt <= txshiftcnt + 1; txshiftcnt <= txshiftcnt + 1;
tx_pin <= txshift(0); tx_pin <= txshift(0);
txshift(6 downto 0) <= txshift(7 downto 1); txshift(6 downto 0) <= txshift(7 downto 1);
end if; end if;
end case; end case;
end if;
end if; end if;
end process; end process;
@ -167,8 +171,6 @@ begin
variable txpopdone : std_logic := '0'; -- latch variable txpopdone : std_logic := '0'; -- latch
variable rxpushdone : std_logic := '0'; -- latch variable rxpushdone : std_logic := '0'; -- latch
begin begin
rxn := rxcnt;
txn := txcnt;
if rst = '1' then if rst = '1' then
for i in 0 to 3 loop for i in 0 to 3 loop
@ -181,6 +183,9 @@ begin
txpopdone := '0'; txpopdone := '0';
rxpushdone := '0'; rxpushdone := '0';
elsif rising_edge(clk) then elsif rising_edge(clk) then
rxn := rxcnt;
txn := txcnt;
dout <= x"0000"; dout <= x"0000";
-- Fifo grooming -- Fifo grooming