Paul Mathieu 102e9cbd07 uart: fix synthesis warnings

2021-04-17 23:07:56 -07:00

base @ e27480fa5d

Add base submodule

2021-02-17 13:23:18 -08:00

cpu

cpu: more instruction pipelining

2021-04-17 23:02:58 -07:00

dsp

dsp: small refactor

2021-03-20 21:27:36 -07:00

first

hello: simplify interconnect

2021-03-12 14:18:37 -08:00

sysbus

Small fixes for synthesis

2021-03-13 21:02:54 -08:00

tools

ld: allow linking to a different offset

2021-04-17 23:05:02 -07:00

uart

uart: fix synthesis warnings

2021-04-17 23:07:56 -07:00

wave

wave: add header

2021-03-13 15:47:24 -08:00

.gitignore

gitignore: a few more things

2021-03-14 12:18:36 -07:00

.gitmodules

Add base submodule

2021-02-17 13:23:18 -08:00

Description

No description provided

2 MiB

Languages

C 69.2%

C++ 15.4%

VHDL 8.1%

Python 5.2%

Tcl 1%

Other 0.8%