diff --git a/uart/uart.vhdl b/uart/uart.vhdl
index 7313d3b..6f6151e 100644
--- a/uart/uart.vhdl
+++ b/uart/uart.vhdl
@@ -32,7 +32,7 @@ end uart;
 -- Mnemonic: receive from the left, transmit to the right
 
 architecture Behavioral of uart is
-  constant BAUD: positive := 115_200;
+  constant BAUD: positive := 1_000_000;
   constant SYSFREQ: natural := 100_000_000;
   constant CLKCNT: natural := SYSFREQ / BAUD;
 
@@ -78,32 +78,34 @@ begin
       for i in 0 to 3 loop
         rxfifo(i) <= x"00";
       end loop;
-    elsif rising_edge(clk) and uarten = '1' then
-      rxpushed <= '0';
+    elsif rising_edge(clk) then
+      if uarten = '1' then
+        rxpushed <= '0';
 
-      case rxstate is
-        when IDLE =>
-          if rx_pin = '0' then  -- start bit!! (hopefully)
-            rxshift <= x"00";
-            rxshiftcnt <= "0000";
-            rxstate <= SHIFT_IN;
-          end if;
-        when SHIFT_IN =>
-          if rxshiftcnt = 8 then
-            -- by now we should be seeing the stop bit, check
-            if rx_pin = '1' then -- all good, push away
-              for i in 2 downto 0 loop  -- right to left
-                rxfifo(i + 1) <= rxfifo(i);
-              end loop;
-              rxfifo(0) <= rxshift;
-              rxpushed <= '1';
+        case rxstate is
+          when IDLE =>
+            if rx_pin = '0' then  -- start bit!! (hopefully)
+              rxshift <= x"00";
+              rxshiftcnt <= "0000";
+              rxstate <= SHIFT_IN;
             end if;
-            rxstate <= IDLE;  -- either way, we're done
-          else
-            rxshift <= rx_pin & rxshift(7 downto 1);
-            rxshiftcnt <= rxshiftcnt + 1;
-          end if;
-      end case;
+          when SHIFT_IN =>
+            if rxshiftcnt = 8 then
+              -- by now we should be seeing the stop bit, check
+              if rx_pin = '1' then -- all good, push away
+                for i in 2 downto 0 loop  -- right to left
+                  rxfifo(i + 1) <= rxfifo(i);
+                end loop;
+                rxfifo(0) <= rxshift;
+                rxpushed <= '1';
+              end if;
+              rxstate <= IDLE;  -- either way, we're done
+            else
+              rxshift <= rx_pin & rxshift(7 downto 1);
+              rxshiftcnt <= rxshiftcnt + 1;
+            end if;
+        end case;
+      end if;
     end if;
   end process;
 
@@ -117,30 +119,32 @@ begin
       txshift <= x"00";
       txshiftcnt <= "0000";
       tx_pin <= '1';
-    elsif rising_edge(clk) and uarten = '1' then
-      txpopped <= '0';
+    elsif rising_edge(clk) then
+      if uarten = '1' then
+        txpopped <= '0';
 
-      case txstate is
-        when IDLE =>
-          if txcnt > 0 then
-            txshiftcnt <= "0000";
-            tx_pin <= '0';  -- start bit
-            txstate <= SHIFT_OUT;
-            txshift <= txfifo(0);
-            txpopped <= '1';
-          else
-            tx_pin <= '1';
-          end if;
-        when SHIFT_OUT =>
-          if txshiftcnt = 8 then
-            tx_pin <= '1';
-            txstate <= IDLE;
-          else
-            txshiftcnt <= txshiftcnt + 1;
-            tx_pin <= txshift(0);
-            txshift(6 downto 0) <= txshift(7 downto 1);
-          end if;
-      end case;
+        case txstate is
+          when IDLE =>
+            if txcnt > 0 then
+              txshiftcnt <= "0000";
+              tx_pin <= '0';  -- start bit
+              txstate <= SHIFT_OUT;
+              txshift <= txfifo(0);
+              txpopped <= '1';
+            else
+              tx_pin <= '1';
+            end if;
+          when SHIFT_OUT =>
+            if txshiftcnt = 8 then
+              tx_pin <= '1';
+              txstate <= IDLE;
+            else
+              txshiftcnt <= txshiftcnt + 1;
+              tx_pin <= txshift(0);
+              txshift(6 downto 0) <= txshift(7 downto 1);
+            end if;
+        end case;
+      end if;
     end if;
   end process;
 
@@ -167,8 +171,6 @@ begin
     variable txpopdone  : std_logic := '0'; -- latch
     variable rxpushdone : std_logic := '0'; -- latch
   begin
-    rxn := rxcnt;
-    txn := txcnt;
 
     if rst = '1' then
       for i in 0 to 3 loop
@@ -181,6 +183,9 @@ begin
       txpopdone := '0';
       rxpushdone := '0';
     elsif rising_edge(clk) then
+      rxn := rxcnt;
+      txn := txcnt;
+
       dout <= x"0000";
 
       -- Fifo grooming