2021-03-13 23:50:25 +00:00
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all: sim rom
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sim: dsp_test.ghw
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rom: boot_rom.gen.vhdl
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2021-03-15 01:08:53 +00:00
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bin: ../lab/dsp/au_base_project.runs/impl_1/au_top.bin
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2021-03-13 23:50:25 +00:00
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CC = ../bin/cc
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LD = ../bin/ld
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CFLAGS = -I../wave -I../uart
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2021-04-18 06:13:20 +00:00
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offset = $(shell printf "%d" 0x1100)
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2021-07-26 07:00:26 +00:00
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test_boot_rom.gen.vhdl: bootloader.o ../uart/uart.o
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2021-04-18 06:13:20 +00:00
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boot_rom.gen.vhdl: bootloader.o ../uart/uart.o
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2021-07-26 07:00:26 +00:00
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# hello.bin: hello.o ../uart/uart.o
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# synth.bin: synth.o ../uart/uart.o
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# echo.bin: echo.o ../uart/uart.o
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# bootloader.bin: bootloader.o ../uart/uart.o
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2021-03-13 23:50:25 +00:00
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2021-04-24 15:57:55 +00:00
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sim_sources = dsp_test.vhdl test_boot_rom.gen.vhdl
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sources = dsp.vhdl ram.vhdl \
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2021-03-14 19:14:55 +00:00
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../cpu/cpu.vhdl ../cpu/reg.vhdl ../cpu/alu.vhdl \
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2021-03-13 23:50:25 +00:00
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$(wildcard ../wave/*.vhdl) \
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$(wildcard ../sysbus/*.vhdl) \
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2021-04-18 06:09:30 +00:00
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../uart/uart.vhdl
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2021-03-13 23:50:25 +00:00
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2021-03-15 01:08:53 +00:00
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../lab/dsp/au_base_project.runs/impl_1/au_top.bin: ../lab/dsp/au_base_project.runs/synth_1/au_top.dcp
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../lab/dsp/au_base_project.runs/impl_1/runme.sh
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2021-04-24 15:57:55 +00:00
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../lab/dsp/au_base_project.runs/synth_1/au_top.dcp: $(sources) boot_rom.gen.vhdl
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2021-03-15 01:08:53 +00:00
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../lab/dsp/au_base_project.runs/synth_1/runme.sh
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2021-03-13 23:50:25 +00:00
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2021-07-26 07:00:26 +00:00
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%.bin: %.o ../uart/uart.o
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2021-04-18 06:13:20 +00:00
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$(LD) -o $@ --offset $(offset) $^
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2021-03-13 23:50:25 +00:00
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%.gen.vhdl:
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$(LD) -o $@ --vhdl $*.vhdl.in $^
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%.ghw: work-obj93.cf
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ghdl -r $* --wave=$@ --assert-level=error
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work-obj93.cf: $(sim_sources) $(sources)
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ghdl -a $^
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2021-03-15 01:08:53 +00:00
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PHONY: bin sim rom clean
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2021-03-13 23:50:25 +00:00
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clean:
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2021-04-18 06:13:20 +00:00
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rm -rf *.o *.gen.vhdl *.ghw work-obj93.cf *.bin
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2021-03-13 23:50:25 +00:00
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.DELETE_ON_ERROR:
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.PRECIOUS: %.ghw
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