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base@e27480fa5d
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Add base submodule
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2021-02-17 13:23:18 -08:00 |
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cpu
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cpu: more instruction pipelining
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2021-04-17 23:02:58 -07:00 |
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dsp
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dsp: allow fetching instructions from SRAM
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2021-04-17 23:11:04 -07:00 |
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first
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hello: simplify interconnect
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2021-03-12 14:18:37 -08:00 |
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sysbus
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Small fixes for synthesis
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2021-03-13 21:02:54 -08:00 |
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tools
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ld: allow linking to a different offset
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2021-04-17 23:05:02 -07:00 |
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uart
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uart: fix synthesis warnings
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2021-04-17 23:07:56 -07:00 |
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wave
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wave: add header
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2021-03-13 15:47:24 -08:00 |
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.gitignore
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gitignore: a few more things
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2021-03-14 12:18:36 -07:00 |
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.gitmodules
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Add base submodule
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2021-02-17 13:23:18 -08:00 |
