32 lines
490 B
Verilog
32 lines
490 B
Verilog
/*
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Parameters:
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STAGES = 4
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*/
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module reset_conditioner (
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input clk,
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input rin,
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output reg rout
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);
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localparam STAGES = 3'h4;
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reg [3:0] M_stage_d, M_stage_q = 4'hf;
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always @* begin
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M_stage_d = M_stage_q;
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M_stage_d = {M_stage_q[0+2-:3], 1'h0};
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rout = M_stage_q[3+0-:1];
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end
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always @(posedge clk) begin
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if (rin == 1'b1) begin
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M_stage_q <= 4'hf;
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end else begin
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M_stage_q <= M_stage_d;
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end
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end
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endmodule
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