Paul Mathieu 47059c1c15 Add vivado base project submodule

2022-05-07 21:44:45 -07:00

Au-Base-Project @ e27480fa5d

Add vivado base project submodule

2022-05-07 21:44:45 -07:00

base @ e27480fa5d

Add base submodule

2021-02-17 13:23:18 -08:00

cpu

cpu: more instruction pipelining

2021-04-17 23:02:58 -07:00

dsp

dsp: update test

2021-07-26 00:04:53 -07:00

first

hello: simplify interconnect

2021-03-12 14:18:37 -08:00

sysbus

sysbus: fix concurrent read & writes

2021-04-24 08:55:51 -07:00

tools

as: fix empty param list

2022-05-07 11:34:35 -07:00

uart

uart: RX adaptive clock and over sampling

2021-07-25 23:50:53 -07:00

wave

wave: fix write to busy sysbus

2021-04-24 08:55:23 -07:00

.gitignore

gitignore: add *.pyc

2022-05-07 11:35:49 -07:00

.gitmodules

Add vivado base project submodule

2022-05-07 21:44:45 -07:00

Description

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2 MiB

Languages

C 69.7%

C++ 15.5%

VHDL 7.5%

Python 5.2%

Tcl 1%

Other 0.9%