Paul Mathieu 36bc1417b6 cpu: more instruction pipelining ... This is needed to make WNS room for fetching instructions from SRAM.		2021-04-17 23:02:58 -07:00
..
as.ebnf	Initial commit	2021-02-17 13:20:30 -08:00
as.py	cpu: more instruction pipelining	2021-04-17 23:02:58 -07:00
cc.ebnf	cc: fix typo	2021-03-20 21:25:01 -07:00
cc.py	cpu: more instruction pipelining	2021-04-17 23:02:58 -07:00
crt0.s	Fix initial stack pointer	2021-02-22 20:34:54 -08:00
ld.py	ld: now generates a full rom vhdl from template	2021-03-13 15:44:48 -08:00
makefile	Initial commit	2021-02-17 13:20:30 -08:00
obj.proto	Initial commit	2021-02-17 13:20:30 -08:00
requirements.txt	Initial commit	2021-02-17 13:20:30 -08:00