cpu: make BEQ and BNEQ only PC-relative
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24c6831813
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d1d0e421ce
@ -186,16 +186,16 @@ begin
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alu_b <= reg_q(regn_1);
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reg_d(15)(0) <= alu_flag;
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when "1101" => -- BEQ [rn, imm] (jump to [rn, imm] if flag is set, imm is signed 8 bits)
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when "1101" => -- BEQ imm (jump to [pc, imm] if flag is set, imm is signed 12 bits)
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if reg_q(15)(0) = '1' then
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reg_d(14) <= std_logic_vector(signed(reg_q(regn_0)) + signed(inst(7 downto 0) & '0'));
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reg_d(14) <= std_logic_vector(signed(reg_q(14)) + signed(inst(11 downto 0) & '0'));
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cpu_state_next <= BRANCH;
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end if;
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when "1110" => -- SET rd, imm (rd := imm, imm is 8 bit)
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reg_d(regn_0) <= x"00" & inst(7 downto 0);
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when "1111" => -- BNEQ [rn, imm]
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when "1111" => -- BNEQ imm
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if reg_q(15)(0) = '0' then
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reg_d(14) <= std_logic_vector(signed(reg_q(regn_0)) + signed(inst(7 downto 0) & '0'));
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reg_d(14) <= std_logic_vector(signed(reg_q(14)) + signed(inst(11 downto 0) & '0'));
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cpu_state_next <= BRANCH;
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end if;
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@ -22,9 +22,9 @@ opcodes = {
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'shr' : lambda p0, p1, p2: f'a{p0:x}{p1:x}{p2:x}',
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'mul' : lambda p0, p1, p2: f'b{p0:x}{p1:x}{p2:x}',
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'cmp' : lambda p0, p1: f'c{p0:x}{p1:x}0',
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'beq' : lambda p0, p1: f'd{p0:x}{(p1 >> 1)&0xff:02x}',
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'beq' : lambda p0, p1: f'd{(p1 >> 1)&0xfff:03x}',
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'set' : lambda p0, p1: f'e{p0:x}{p1&0xff:02x}',
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'bneq' : lambda p0, p1: f'f{p0:x}{(p1 >> 1)&0xff:02x}',
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'bneq' : lambda p0, p1: f'f{(p1 >> 1)&0xfff:03x}',
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'.word': lambda p0: f'{p0:04x}',
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}
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