From d1d0e421ce6f4f40a27be46a61911aec63d13047 Mon Sep 17 00:00:00 2001 From: Paul Mathieu Date: Sun, 14 Mar 2021 12:14:29 -0700 Subject: [PATCH] cpu: make BEQ and BNEQ only PC-relative --- cpu/cpu.vhdl | 8 ++++---- tools/as.py | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/cpu/cpu.vhdl b/cpu/cpu.vhdl index 1d0997e..23ac1be 100644 --- a/cpu/cpu.vhdl +++ b/cpu/cpu.vhdl @@ -186,16 +186,16 @@ begin alu_b <= reg_q(regn_1); reg_d(15)(0) <= alu_flag; - when "1101" => -- BEQ [rn, imm] (jump to [rn, imm] if flag is set, imm is signed 8 bits) + when "1101" => -- BEQ imm (jump to [pc, imm] if flag is set, imm is signed 12 bits) if reg_q(15)(0) = '1' then - reg_d(14) <= std_logic_vector(signed(reg_q(regn_0)) + signed(inst(7 downto 0) & '0')); + reg_d(14) <= std_logic_vector(signed(reg_q(14)) + signed(inst(11 downto 0) & '0')); cpu_state_next <= BRANCH; end if; when "1110" => -- SET rd, imm (rd := imm, imm is 8 bit) reg_d(regn_0) <= x"00" & inst(7 downto 0); - when "1111" => -- BNEQ [rn, imm] + when "1111" => -- BNEQ imm if reg_q(15)(0) = '0' then - reg_d(14) <= std_logic_vector(signed(reg_q(regn_0)) + signed(inst(7 downto 0) & '0')); + reg_d(14) <= std_logic_vector(signed(reg_q(14)) + signed(inst(11 downto 0) & '0')); cpu_state_next <= BRANCH; end if; diff --git a/tools/as.py b/tools/as.py index b07c769..f95bb90 100644 --- a/tools/as.py +++ b/tools/as.py @@ -22,9 +22,9 @@ opcodes = { 'shr' : lambda p0, p1, p2: f'a{p0:x}{p1:x}{p2:x}', 'mul' : lambda p0, p1, p2: f'b{p0:x}{p1:x}{p2:x}', 'cmp' : lambda p0, p1: f'c{p0:x}{p1:x}0', - 'beq' : lambda p0, p1: f'd{p0:x}{(p1 >> 1)&0xff:02x}', + 'beq' : lambda p0, p1: f'd{(p1 >> 1)&0xfff:03x}', 'set' : lambda p0, p1: f'e{p0:x}{p1&0xff:02x}', - 'bneq' : lambda p0, p1: f'f{p0:x}{(p1 >> 1)&0xff:02x}', + 'bneq' : lambda p0, p1: f'f{(p1 >> 1)&0xfff:03x}', '.word': lambda p0: f'{p0:04x}', }