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dsp: allow fetching instructions from SRAM

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This commit is contained in:
Paul Mathieu
2021-04-17 23:09:30 -07:00
parent 102e9cbd07
commit a864ca3d7e
4 changed files with 159 additions and 50 deletions
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39
dsp/dsp_test.vhdl
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@@ -34,7 +34,12 @@ architecture rtl of dsp_test is
signal pdmout0: std_logic;
type str is array(integer range <>) of std_logic_vector(7 downto 0);
signal blarg: str(0 to 4) := (x"61", x"64", x"64", x"61", x"64");
signal prog: str(0 to 7) := (
x"63", x"11", x"00", x"04", x"e0", x"00", x"5e", x"00");
signal jump: str(0 to 2) := (
x"6a", x"11", x"00");
constant UART_PERIOD: time := 1000 ns;
begin
dut: dsp port map(clk => clk, rst => rst,
@@ -56,21 +61,41 @@ begin
rst <= '0';
wait for 20 us;
for i in 0 to 4 loop
for i in 0 to 7 loop
uart_rx <= '0'; -- start bit
wait for 8681 ns;
wait for UART_PERIOD;
for j in 0 to 7 loop
uart_rx <= blarg(i)(j);
wait for 8681 ns;
uart_rx <= prog(i)(j);
wait for UART_PERIOD;
end loop;
uart_rx <= '1'; -- stop bit
wait for 8681 ns;
wait for UART_PERIOD;
end loop;
wait for 2 ms;
wait for 2 us;
assert(led = x"f0") report "Fail prog" severity error;
for i in 0 to 2 loop
uart_rx <= '0'; -- start bit
wait for UART_PERIOD;
for j in 0 to 7 loop
uart_rx <= jump(i)(j);
wait for UART_PERIOD;
end loop;
uart_rx <= '1'; -- stop bit
wait for UART_PERIOD;
end loop;
wait for 2 us;
assert(led = x"01") report "Fail prog" severity error;
assert false report "Test done." severity note;