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cpu: streamline hold a little

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This commit is contained in:
Paul Mathieu 2021-03-14 18:08:13 -07:00
parent 48ffd4eb6d
commit 7ba6746ddd
1 changed files with 2 additions and 3 deletions
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5
cpu/cpu.vhdl
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@ -106,7 +106,6 @@ begin
load_reg_next <= load_reg; load_reg_next <= load_reg;
load_addr_next <= load_addr; load_addr_next <= load_addr;
hold_inst_next <= hold_inst;
case cpu_state is case cpu_state is
when RUN => when RUN =>
@ -132,6 +131,8 @@ begin
reg_d(14) <= std_logic_vector(unsigned(reg_q(14)) + 2); reg_d(14) <= std_logic_vector(unsigned(reg_q(14)) + 2);
end case; end case;
hold_inst_next <= inst;
regn_0 := to_integer(unsigned(inst(11 downto 8))); regn_0 := to_integer(unsigned(inst(11 downto 8)));
regn_1 := to_integer(unsigned(inst(7 downto 4))); regn_1 := to_integer(unsigned(inst(7 downto 4)));
regn_2 := to_integer(unsigned(inst(3 downto 0))); regn_2 := to_integer(unsigned(inst(3 downto 0)));
@ -141,7 +142,6 @@ begin
when "0001" => -- LOAD rn, [rm, imm] (imm is signed 4 bits) when "0001" => -- LOAD rn, [rm, imm] (imm is signed 4 bits)
if mem_busy = '1' then if mem_busy = '1' then
reg_d(14) <= reg_q(14); -- halt the prefetcher reg_d(14) <= reg_q(14); -- halt the prefetcher
hold_inst_next <= inst;
cpu_state_next <= WAIT_MEM; cpu_state_next <= WAIT_MEM;
else else
mem_read <= '1'; mem_read <= '1';
@ -156,7 +156,6 @@ begin
when "0010" => -- STORE rn, [rm, imm] when "0010" => -- STORE rn, [rm, imm]
if mem_busy = '1' then if mem_busy = '1' then
reg_d(14) <= reg_q(14); -- halt the prefetcher reg_d(14) <= reg_q(14); -- halt the prefetcher
hold_inst_next <= inst;
cpu_state_next <= WAIT_MEM; cpu_state_next <= WAIT_MEM;
else else
mem_write <= '1'; mem_write <= '1';