diff --git a/cpu/cpu.vhdl b/cpu/cpu.vhdl
index 23ac1be..b5c96ed 100644
--- a/cpu/cpu.vhdl
+++ b/cpu/cpu.vhdl
@@ -106,7 +106,6 @@ begin
 
     load_reg_next <= load_reg;
     load_addr_next <= load_addr;
-    hold_inst_next <= hold_inst;
 
     case cpu_state is
       when RUN =>
@@ -132,6 +131,8 @@ begin
         reg_d(14) <= std_logic_vector(unsigned(reg_q(14)) + 2);
     end case;
 
+    hold_inst_next <= inst;
+
     regn_0 := to_integer(unsigned(inst(11 downto 8)));
     regn_1 := to_integer(unsigned(inst(7 downto 4)));
     regn_2 := to_integer(unsigned(inst(3 downto 0)));
@@ -141,7 +142,6 @@ begin
       when "0001" => -- LOAD rn, [rm, imm] (imm is signed 4 bits)
         if mem_busy = '1' then
           reg_d(14) <= reg_q(14);  -- halt the prefetcher
-          hold_inst_next <= inst;
           cpu_state_next <= WAIT_MEM;
         else
           mem_read <= '1';
@@ -156,7 +156,6 @@ begin
       when "0010" => -- STORE rn, [rm, imm]
         if mem_busy = '1' then
           reg_d(14) <= reg_q(14);  -- halt the prefetcher
-          hold_inst_next <= inst;
           cpu_state_next <= WAIT_MEM;
         else
           mem_write <= '1';