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hello: simplify interconnect

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This commit is contained in:
Paul Mathieu 2021-03-12 14:18:37 -08:00
parent 50dedf1dd8
commit 3b56750a73
1 changed files with 61 additions and 60 deletions
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33
first/hello.vhdl
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@ -4,7 +4,8 @@ use ieee.numeric_std.all;
use std.textio.all;
entity hello is
port(
port
(
clk: in std_logic;
rst: in std_logic;
@ -17,7 +18,8 @@ end hello;
architecture rtl of hello is
component cpu is port(
component cpu is port
(
clk: in std_logic;
rst: in std_logic;
@ -55,12 +57,14 @@ architecture rtl of hello is
--END COMPONENT;
component ram is
generic (
generic
(
addressWidth : in positive := 16;
busWidth : in positive := 16;
size : in positive := 1024
);
port (
port
(
clk : in std_logic;
address : in std_logic_vector(addressWidth - 1 downto 0);
writeEnable : in std_logic;
@ -69,7 +73,8 @@ architecture rtl of hello is
);
end component;
component boot_rom is port (
component boot_rom is port
(
clk: in std_logic;
code_addr : in std_logic_vector(15 downto 0);
@ -128,7 +133,8 @@ begin
-- system map
-- 0x0000 - 0x0fff ROM
-- 0x1000 - 0x1fff RAM
-- 0xc000 - 0xc000 GPIO?
-- 0xc000 - 0xc00f LED
-- 0xc010 - 0xc01f UART
led <= led_r;
@ -148,27 +154,24 @@ begin
bus_miso <= x"0000";
rom_data_addr <= x"0000";
rom_data_addr <= bus_addr and x"0fff";
mem_addr <= x"0000";
mem_in <= x"0000";
mem_addr <= bus_addr and x"0fff";
mem_in <= bus_mosi;
mem_write <= '0';
led_next <= led_r;
uart_din <= x"0000";
uart_addr <= x"0000";
uart_din <= bus_mosi;
uart_addr <= bus_addr and x"000f";
uart_we <= '0';
uart_re <= '0';
case bus_addr(15 downto 12) is
when x"0" =>
bus_miso <= rom_data_out;
rom_data_addr <= bus_addr and x"0fff";
when x"1" =>
mem_in <= bus_mosi;
bus_miso <= mem_out;
mem_addr <= bus_addr and x"0fff";
mem_write <= bus_write;
when x"c" =>
case bus_addr(7 downto 4) is
@ -177,9 +180,7 @@ begin
led_next <= bus_mosi(7 downto 0);
end if;
when x"1" => -- UART
uart_din <= bus_mosi;
bus_miso <= uart_dout;
uart_addr <= bus_addr and x"000f";
uart_we <= bus_write;
uart_re <= bus_read;
when others =>