diff --git a/first/hello.vhdl b/first/hello.vhdl
index 3d15e2a..f4ecdc4 100644
--- a/first/hello.vhdl
+++ b/first/hello.vhdl
@@ -4,32 +4,34 @@ use ieee.numeric_std.all;
 use std.textio.all;
 
 entity hello is
-  port(
-        clk: in std_logic;
-        rst: in std_logic;
+  port
+  (
+    clk: in std_logic;
+    rst: in std_logic;
 
-        led: out std_logic_vector(7 downto 0);
+    led: out std_logic_vector(7 downto 0);
 
-        uart_rx: in std_logic;
-        uart_tx: out std_logic
-      );
+    uart_rx: in std_logic;
+    uart_tx: out std_logic
+  );
 end hello;
 
 architecture rtl of hello is
 
-  component cpu is port(
-                         clk: in std_logic;
-                         rst: in std_logic;
+  component cpu is port
+    (
+      clk: in std_logic;
+      rst: in std_logic;
 
-                         code_data: in std_logic_vector(15 downto 0);
-                         code_addr: out std_logic_vector(15 downto 0);
+      code_data: in std_logic_vector(15 downto 0);
+      code_addr: out std_logic_vector(15 downto 0);
 
-                         mem_in: in std_logic_vector(15 downto 0);
-                         mem_out: out std_logic_vector(15 downto 0);
-                         mem_addr: out std_logic_vector(15 downto 0);
-                         mem_write: out std_logic;
-                         mem_read: out std_logic
-                       );
+      mem_in: in std_logic_vector(15 downto 0);
+      mem_out: out std_logic_vector(15 downto 0);
+      mem_addr: out std_logic_vector(15 downto 0);
+      mem_write: out std_logic;
+      mem_read: out std_logic
+    );
   end component;
 
 --  component boot_rom IS
@@ -55,48 +57,51 @@ architecture rtl of hello is
 --END COMPONENT;
 
   component ram is
-    generic (
-              addressWidth : in positive := 16;
-              busWidth : in positive := 16;
-              size : in positive := 1024
-            );
-    port (
-           clk : in std_logic;
-           address : in std_logic_vector(addressWidth - 1 downto 0);
-           writeEnable : in std_logic;
-           dataIn : in std_logic_vector(busWidth - 1 downto 0);
-           dataOut : out std_logic_vector(busWidth - 1 downto 0)
-         );
+    generic
+    (
+      addressWidth : in positive := 16;
+      busWidth : in positive := 16;
+      size : in positive := 1024
+    );
+    port
+    (
+      clk : in std_logic;
+      address : in std_logic_vector(addressWidth - 1 downto 0);
+      writeEnable : in std_logic;
+      dataIn : in std_logic_vector(busWidth - 1 downto 0);
+      dataOut : out std_logic_vector(busWidth - 1 downto 0)
+    );
   end component;
 
-  component boot_rom is port (
-                                clk: in std_logic;
+  component boot_rom is port
+    (
+      clk: in std_logic;
 
-                               code_addr : in std_logic_vector(15 downto 0);
-                               code_out : out std_logic_vector(15 downto 0);
+      code_addr : in std_logic_vector(15 downto 0);
+      code_out : out std_logic_vector(15 downto 0);
 
-                               data_addr : in std_logic_vector(15 downto 0);
-                               data_out : out std_logic_vector(15 downto 0)
-                             );
+      data_addr : in std_logic_vector(15 downto 0);
+      data_out : out std_logic_vector(15 downto 0)
+    );
   end component;
 
   component uart is
-  port
-  (
-    clk     : in std_logic;
-    rst     : in std_logic;
+    port
+    (
+      clk     : in std_logic;
+      rst     : in std_logic;
 
     -- hardware
-    rx_pin  : in std_logic;
-    tx_pin  : out std_logic;
+      rx_pin  : in std_logic;
+      tx_pin  : out std_logic;
 
     -- bus interface
-    we      : in std_logic;
-    re      : in std_logic;
-    addr    : in std_logic_vector(15 downto 0);
-    din     : in std_logic_vector(15 downto 0);
-    dout    : out std_logic_vector(15 downto 0)
-  );
+      we      : in std_logic;
+      re      : in std_logic;
+      addr    : in std_logic_vector(15 downto 0);
+      din     : in std_logic_vector(15 downto 0);
+      dout    : out std_logic_vector(15 downto 0)
+    );
   end component;
 
   signal mem_write, mem_read: std_logic;
@@ -128,7 +133,8 @@ begin
   -- system map
   --  0x0000 - 0x0fff  ROM
   --  0x1000 - 0x1fff  RAM
-  --  0xc000 - 0xc000  GPIO?
+  --  0xc000 - 0xc00f  LED
+  --  0xc010 - 0xc01f  UART
 
   led <= led_r;
 
@@ -148,27 +154,24 @@ begin
 
     bus_miso <= x"0000";
 
-    rom_data_addr <= x"0000";
+    rom_data_addr <= bus_addr and x"0fff";
 
-    mem_addr <= x"0000";
-    mem_in <= x"0000";
+    mem_addr <= bus_addr and x"0fff";
+    mem_in <= bus_mosi;
     mem_write <= '0';
 
     led_next <= led_r;
 
-    uart_din <= x"0000";
-    uart_addr <= x"0000";
+    uart_din <= bus_mosi;
+    uart_addr <= bus_addr and x"000f";
     uart_we <= '0';
     uart_re <= '0';
 
     case bus_addr(15 downto 12) is
       when x"0" =>
         bus_miso <= rom_data_out;
-        rom_data_addr <= bus_addr and x"0fff";
       when x"1" =>
-        mem_in <= bus_mosi;
         bus_miso <= mem_out;
-        mem_addr <= bus_addr and x"0fff";
         mem_write <= bus_write;
       when x"c" =>
         case bus_addr(7 downto 4) is
@@ -177,9 +180,7 @@ begin
               led_next <= bus_mosi(7 downto 0);
             end if;
           when x"1" =>  -- UART
-            uart_din <= bus_mosi;
             bus_miso <= uart_dout;
-            uart_addr <= bus_addr and x"000f";
             uart_we <= bus_write;
             uart_re <= bus_read;
           when others =>