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hello: simplify interconnect

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This commit is contained in:
Paul Mathieu 2021-03-12 14:18:37 -08:00
parent 50dedf1dd8
commit 3b56750a73
1 changed files with 61 additions and 60 deletions
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121
first/hello.vhdl
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@ -4,32 +4,34 @@ use ieee.numeric_std.all;
use std.textio.all; use std.textio.all;
entity hello is entity hello is
port( port
clk: in std_logic; (
rst: in std_logic; clk: in std_logic;
rst: in std_logic;
led: out std_logic_vector(7 downto 0); led: out std_logic_vector(7 downto 0);
uart_rx: in std_logic; uart_rx: in std_logic;
uart_tx: out std_logic uart_tx: out std_logic
); );
end hello; end hello;
architecture rtl of hello is architecture rtl of hello is
component cpu is port( component cpu is port
clk: in std_logic; (
rst: in std_logic; clk: in std_logic;
rst: in std_logic;
code_data: in std_logic_vector(15 downto 0); code_data: in std_logic_vector(15 downto 0);
code_addr: out std_logic_vector(15 downto 0); code_addr: out std_logic_vector(15 downto 0);
mem_in: in std_logic_vector(15 downto 0); mem_in: in std_logic_vector(15 downto 0);
mem_out: out std_logic_vector(15 downto 0); mem_out: out std_logic_vector(15 downto 0);
mem_addr: out std_logic_vector(15 downto 0); mem_addr: out std_logic_vector(15 downto 0);
mem_write: out std_logic; mem_write: out std_logic;
mem_read: out std_logic mem_read: out std_logic
); );
end component; end component;
-- component boot_rom IS -- component boot_rom IS
@ -55,48 +57,51 @@ architecture rtl of hello is
--END COMPONENT; --END COMPONENT;
component ram is component ram is
generic ( generic
addressWidth : in positive := 16; (
busWidth : in positive := 16; addressWidth : in positive := 16;
size : in positive := 1024 busWidth : in positive := 16;
); size : in positive := 1024
port ( );
clk : in std_logic; port
address : in std_logic_vector(addressWidth - 1 downto 0); (
writeEnable : in std_logic; clk : in std_logic;
dataIn : in std_logic_vector(busWidth - 1 downto 0); address : in std_logic_vector(addressWidth - 1 downto 0);
dataOut : out std_logic_vector(busWidth - 1 downto 0) writeEnable : in std_logic;
); dataIn : in std_logic_vector(busWidth - 1 downto 0);
dataOut : out std_logic_vector(busWidth - 1 downto 0)
);
end component; end component;
component boot_rom is port ( component boot_rom is port
clk: in std_logic; (
clk: in std_logic;
code_addr : in std_logic_vector(15 downto 0); code_addr : in std_logic_vector(15 downto 0);
code_out : out std_logic_vector(15 downto 0); code_out : out std_logic_vector(15 downto 0);
data_addr : in std_logic_vector(15 downto 0); data_addr : in std_logic_vector(15 downto 0);
data_out : out std_logic_vector(15 downto 0) data_out : out std_logic_vector(15 downto 0)
); );
end component; end component;
component uart is component uart is
port port
( (
clk : in std_logic; clk : in std_logic;
rst : in std_logic; rst : in std_logic;
-- hardware -- hardware
rx_pin : in std_logic; rx_pin : in std_logic;
tx_pin : out std_logic; tx_pin : out std_logic;
-- bus interface -- bus interface
we : in std_logic; we : in std_logic;
re : in std_logic; re : in std_logic;
addr : in std_logic_vector(15 downto 0); addr : in std_logic_vector(15 downto 0);
din : in std_logic_vector(15 downto 0); din : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0) dout : out std_logic_vector(15 downto 0)
); );
end component; end component;
signal mem_write, mem_read: std_logic; signal mem_write, mem_read: std_logic;
@ -128,7 +133,8 @@ begin
-- system map -- system map
-- 0x0000 - 0x0fff ROM -- 0x0000 - 0x0fff ROM
-- 0x1000 - 0x1fff RAM -- 0x1000 - 0x1fff RAM
-- 0xc000 - 0xc000 GPIO? -- 0xc000 - 0xc00f LED
-- 0xc010 - 0xc01f UART
led <= led_r; led <= led_r;
@ -148,27 +154,24 @@ begin
bus_miso <= x"0000"; bus_miso <= x"0000";
rom_data_addr <= x"0000"; rom_data_addr <= bus_addr and x"0fff";
mem_addr <= x"0000"; mem_addr <= bus_addr and x"0fff";
mem_in <= x"0000"; mem_in <= bus_mosi;
mem_write <= '0'; mem_write <= '0';
led_next <= led_r; led_next <= led_r;
uart_din <= x"0000"; uart_din <= bus_mosi;
uart_addr <= x"0000"; uart_addr <= bus_addr and x"000f";
uart_we <= '0'; uart_we <= '0';
uart_re <= '0'; uart_re <= '0';
case bus_addr(15 downto 12) is case bus_addr(15 downto 12) is
when x"0" => when x"0" =>
bus_miso <= rom_data_out; bus_miso <= rom_data_out;
rom_data_addr <= bus_addr and x"0fff";
when x"1" => when x"1" =>
mem_in <= bus_mosi;
bus_miso <= mem_out; bus_miso <= mem_out;
mem_addr <= bus_addr and x"0fff";
mem_write <= bus_write; mem_write <= bus_write;
when x"c" => when x"c" =>
case bus_addr(7 downto 4) is case bus_addr(7 downto 4) is
@ -177,9 +180,7 @@ begin
led_next <= bus_mosi(7 downto 0); led_next <= bus_mosi(7 downto 0);
end if; end if;
when x"1" => -- UART when x"1" => -- UART
uart_din <= bus_mosi;
bus_miso <= uart_dout; bus_miso <= uart_dout;
uart_addr <= bus_addr and x"000f";
uart_we <= bus_write; uart_we <= bus_write;
uart_re <= bus_read; uart_re <= bus_read;
when others => when others =>