Small fixes for synthesis

2021-03-13 21:02:54 -08:00
parent 14dba00fd0
commit 24c6831813
3 changed files with 5 additions and 2 deletions
--- a/sysbus/sysbus.vhdl
+++ b/sysbus/sysbus.vhdl
@@ -58,7 +58,10 @@ begin
    end if;

    pend_next <= pend;
+    pend_addr_next <= pend_addr;
+    pend_wdata_next <= pend_wdata;
    owner_next <= "00";
+    state_next <= IDLE;

    bus_we <= '0';
    bus_re <= '0';