Small fixes for synthesis

2021-03-13 21:02:54 -08:00
parent 14dba00fd0
commit 24c6831813
3 changed files with 5 additions and 2 deletions
--- a/dsp/dsp.vhdl
+++ b/dsp/dsp.vhdl
@@ -232,7 +232,7 @@ begin
    end if;
  end process;

-  process(bus_addr, bus_mosi, bus_write, mem_out, rst, rom_data_out, led_r, bus_read)
+  process(bus_addr, bus_mosi, bus_write, mem_out, rst, rom_data_out, led_r, bus_read, uart_dout)
  begin

    bus_miso <= x"0000";