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uart: make baudrate a generic

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This commit is contained in:
Paul Mathieu 2021-07-25 23:50:09 -07:00
parent 1d36528b2c
commit 1d69c453a8
1 changed files with 6 additions and 1 deletions
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7
uart/uart.vhdl
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@ -3,6 +3,11 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
entity uart is entity uart is
generic
(
baudrate : in natural := 1_000_000
);
port port
( (
clk : in std_logic; clk : in std_logic;
@ -32,7 +37,7 @@ end uart;
-- Mnemonic: receive from the left, transmit to the right -- Mnemonic: receive from the left, transmit to the right
architecture Behavioral of uart is architecture Behavioral of uart is
constant BAUD: positive := 1_000_000; constant BAUD: positive := baudrate;
constant SYSFREQ: natural := 100_000_000; constant SYSFREQ: natural := 100_000_000;
constant CLKCNT: natural := SYSFREQ / BAUD; constant CLKCNT: natural := SYSFREQ / BAUD;