diff --git a/uart/uart.vhdl b/uart/uart.vhdl
index 6f6151e..0daa97e 100644
--- a/uart/uart.vhdl
+++ b/uart/uart.vhdl
@@ -3,6 +3,11 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 entity uart is
+  generic
+  (
+    baudrate : in natural := 1_000_000
+  );
+
   port
   (
     clk     : in std_logic;
@@ -32,7 +37,7 @@ end uart;
 -- Mnemonic: receive from the left, transmit to the right
 
 architecture Behavioral of uart is
-  constant BAUD: positive := 1_000_000;
+  constant BAUD: positive := baudrate;
   constant SYSFREQ: natural := 100_000_000;
   constant CLKCNT: natural := SYSFREQ / BAUD;