synth/first/top.vhdl

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-- Company: 
-- Engineer: 
-- 
-- Create Date: 02/13/2021 12:09:57 AM
-- Design Name: 
-- Module Name: top - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity top is
    Port ( clk : in STD_LOGIC;
           rst_n : in STD_LOGIC;
           led : out STD_LOGIC_VECTOR (7 downto 0);
                                        usb_rx: in std_logic;
                             usb_tx: out std_logic
           );
end top;

architecture Behavioral of top is
component hello is port(
                         clk: in std_logic;
                         rst: in std_logic;
                         
                             led: out std_logic_vector(7 downto 0);
                     
        uart_rx: in std_logic;
        uart_tx: out std_logic        
                          
                         );
end component;

component reset_conditioner is port(
clk: in std_logic;
rin: in std_logic;
rout: out std_logic
);
end component;

signal rst, rstraw: std_logic;

begin

rstraw <= not rst_n;
reset: reset_conditioner port map(clk => clk, rin => rstraw, rout => rst);
stuff: hello port map(clk => clk, rst => rst, led => led,
                      uart_rx => usb_rx, uart_tx => usb_tx);


end Behavioral;