50 lines
1.1 KiB
VHDL
50 lines
1.1 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity boot_rom is
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generic
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(
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addressWidth : in positive := 16;
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busWidth : in positive := 16
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);
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port
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(
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clk: in std_logic;
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code_addr : in std_logic_vector(15 downto 0);
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code_out : out std_logic_vector(15 downto 0);
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data_addr : in std_logic_vector(15 downto 0);
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data_out : out std_logic_vector(15 downto 0)
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);
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end boot_rom;
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architecture Behavioral of boot_rom is
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constant alignment: positive := busWidth / 8;
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constant romsize: natural := $nwords;
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type romtype is array(0 to romsize - 1) of std_logic_vector(15 downto 0);
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signal romdata: romtype := (
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$words
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);
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begin
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process(clk) is
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variable code_index: natural;
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variable data_index: natural;
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begin
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if rising_edge(clk) then
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code_index := to_integer(unsigned(code_addr)) / alignment;
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if code_index < romsize then
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code_out <= romdata(code_index);
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else
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code_out <= x"0000";
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end if;
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data_index := to_integer(unsigned(data_addr)) / alignment;
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data_out <= romdata(data_index);
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end if;
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end process;
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end Behavioral;
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