14dba00fd0
With: - LED control - UART - PDM out - square wave generator (DMA to PDM out (was it really necessary?)) - sample program that plays a square wave from UART values
81 lines
1.6 KiB
VHDL
81 lines
1.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity dsp_test is
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end dsp_test;
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architecture rtl of dsp_test is
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component clock is port(clk: out std_logic);
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end component;
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component dsp is
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port(
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clk: in std_logic;
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rst: in std_logic;
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led: out std_logic_vector(7 downto 0);
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uart_rx: in std_logic;
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uart_tx: out std_logic;
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pdmout0_pin: out std_logic
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);
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end component;
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signal finished, clk, rst: std_logic := '0';
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signal led: std_logic_vector(7 downto 0);
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signal uart_rx: std_logic;
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signal uart_tx: std_logic;
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signal pdmout0: std_logic;
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type str is array(integer range <>) of std_logic_vector(7 downto 0);
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signal blarg: str(0 to 4) := (x"61", x"64", x"64", x"61", x"64");
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begin
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dut: dsp port map(clk => clk, rst => rst,
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led => led, uart_rx => uart_rx, uart_tx => uart_tx,
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pdmout0_pin => pdmout0);
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clk <= not clk after 5 ns when finished /= '1' else '0';
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process
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begin
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rst <= '1';
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uart_rx <= '1';
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wait for 15 ns;
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assert(led=x"00") report "Fail rst" severity error;
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rst <= '0';
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wait for 20 us;
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for i in 0 to 4 loop
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uart_rx <= '0'; -- start bit
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wait for 8681 ns;
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for j in 0 to 7 loop
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uart_rx <= blarg(i)(j);
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wait for 8681 ns;
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end loop;
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uart_rx <= '1'; -- stop bit
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wait for 8681 ns;
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end loop;
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wait for 2 ms;
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assert false report "Test done." severity note;
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finished <= '1';
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wait;
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end process;
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end rtl;
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