56 lines
1.2 KiB
VHDL
56 lines
1.2 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 02/13/2021 01:13:18 PM
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-- Design Name:
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-- Module Name: register - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity reg is
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Port ( d : in STD_LOGIC_VECTOR (15 downto 0);
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q : out STD_LOGIC_VECTOR (15 downto 0);
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rst : in STD_LOGIC;
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clk : in STD_LOGIC);
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end reg;
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architecture Behavioral of reg is
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begin
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process(clk, rst) is
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begin
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if (rst = '1') then
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q <= x"0000";
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else
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if rising_edge(clk) then
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q <= d;
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end if;
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end if;
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end process;
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end Behavioral;
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