synth/dsp/makefile
2021-04-17 23:11:04 -07:00

46 lines
990 B
Makefile

all: sim rom
sim: dsp_test.ghw
rom: boot_rom.gen.vhdl
bin: ../lab/dsp/au_base_project.runs/impl_1/au_top.bin
CC = ../bin/cc
LD = ../bin/ld
CFLAGS = -I../wave -I../uart
boot_rom.gen.vhdl: main.o ../uart/uart.o
sim_sources = dsp_test.vhdl
sources = boot_rom.gen.vhdl dsp.vhdl ram.vhdl \
../cpu/cpu.vhdl ../cpu/reg.vhdl ../cpu/alu.vhdl \
$(wildcard ../wave/*.vhdl) \
$(wildcard ../sysbus/*.vhdl) \
../uart/uart.vhdl
../lab/dsp/au_base_project.runs/impl_1/au_top.bin: ../lab/dsp/au_base_project.runs/synth_1/au_top.dcp
../lab/dsp/au_base_project.runs/impl_1/runme.sh
../lab/dsp/au_base_project.runs/synth_1/au_top.dcp: $(sources)
../lab/dsp/au_base_project.runs/synth_1/runme.sh
%.gen.vhdl:
$(LD) -o $@ --vhdl $*.vhdl.in $^
%.ghw: work-obj93.cf
ghdl -r $* --wave=$@ --assert-level=error
work-obj93.cf: $(sim_sources) $(sources)
ghdl -a $^
PHONY: bin sim rom clean
clean:
rm -rf *.o *.gen.vhdl *.ghw work-obj93.cf
.DELETE_ON_ERROR:
.PRECIOUS: %.ghw