138 lines
3.0 KiB
VHDL
138 lines
3.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- some kind of square wave generator, writing 16-bit samples
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-- to a memory address using DMA periodically
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entity square is
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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-- bus slave interface
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s_we : in std_logic;
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s_addr : in std_logic_vector(15 downto 0);
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s_din : in std_logic_vector(15 downto 0);
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-- bus master interface (DMA!!)
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m_busy : in std_logic;
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m_we : out std_logic;
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m_addr : out std_logic_vector(15 downto 0);
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m_dout : out std_logic_vector(15 downto 0)
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);
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end square;
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--
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-- Mem layout:
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-- 0x00: 16-bit unsigned period (units of 256 clock cycles)
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-- 0x02: 16-bit unsigned high value
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-- 0x04: 16-bit unsigned low value
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-- 0x06: 16-bit output address
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-- 0x08: flags: [enabled]
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architecture Behavioral of square is
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-- all registers
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signal period, hi_val, lo_val, out_addr: std_logic_vector(15 downto 0);
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signal enabled: std_logic;
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signal counter: unsigned(23 downto 0);
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signal active: std_logic;
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begin
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-- counter process
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-- drives counter, active
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process(clk, rst)
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begin
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if rst = '1' then
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counter <= to_unsigned(0, 24);
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active <= '0';
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elsif rising_edge(clk) then
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active <= '0';
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counter <= to_unsigned(0, 24);
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if enabled = '1' and unsigned(period) /= 0 then
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if counter(22 downto 7) = unsigned(period) then
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active <= '1';
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else
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counter <= counter + 1;
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end if;
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end if;
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end if;
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end process;
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-- signal generation
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-- drives m_we, m_addr, m_dout
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process(clk, rst)
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variable high: std_logic;
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variable deferred: std_logic;
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begin
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if rst = '1' then
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m_we <= '0';
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m_addr <= x"0000";
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m_dout <= x"0000";
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high := '0';
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deferred := '0';
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elsif rising_edge(clk) then
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m_we <= '0';
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if enabled = '1' then
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if active = '1' and m_busy = '1' then
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deferred := '1';
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elsif deferred = '1' or (active = '1' and m_busy = '0') then
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m_we <= '1';
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m_addr <= out_addr;
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if high = '1' then
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m_dout <= hi_val;
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else
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m_dout <= lo_val;
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end if;
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high := not high;
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deferred := '0';
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end if;
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end if;
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end if;
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end process;
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-- Bus slave process
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-- drives period, value, out_addr, enabled
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process(clk, rst)
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begin
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if rst = '1' then
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period <= x"0000";
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hi_val <= x"0000";
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lo_val <= x"0000";
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out_addr <= x"0000";
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enabled <= '0';
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elsif rising_edge(clk) then
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if s_we = '1' then
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case s_addr(3 downto 0) is
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when x"0" =>
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period <= s_din;
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when x"2" =>
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hi_val <= s_din;
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when x"4" =>
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lo_val <= s_din;
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when x"6" =>
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out_addr <= s_din;
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when x"8" =>
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enabled <= s_din(0);
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when others =>
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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