58 lines
1.4 KiB
VHDL
58 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Aligned IO only.
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-- Unaligned addra bits are ignored.
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-- E.g. on a 16-bit bus, last addra bit is ignored.
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entity ram is
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generic
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(
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addressWidth : in positive := 16;
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busWidth : in positive := 16;
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size : in positive := 1024
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);
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port
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(
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clk : in std_logic;
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-- port A
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addra : in std_logic_vector(addressWidth - 1 downto 0);
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wea : in std_logic;
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dina : in std_logic_vector(busWidth - 1 downto 0);
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douta : out std_logic_vector(busWidth - 1 downto 0);
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-- port B (read only)
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addrb : in std_logic_vector(addressWidth - 1 downto 0);
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doutb : out std_logic_vector(busWidth - 1 downto 0)
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);
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end ram;
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architecture Behavioral of ram is
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constant alignment : positive := busWidth / 8;
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constant ramSize : positive := size / alignment;
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type ramType is array(natural range <>) of std_logic_vector(busWidth - 1 downto 0);
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subtype ramRange is natural range 0 to ramSize;
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signal mem : ramType(ramRange);
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begin
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process(clk)
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variable indexa, indexb : ramRange;
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begin
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if (rising_edge(clk))
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then
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indexa := to_integer(unsigned(addra)) / alignment;
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indexb := to_integer(unsigned(addrb)) / alignment;
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if (wea = '1')
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then
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mem(indexa) <= dina;
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end if;
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douta <= mem(indexa);
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doutb <= mem(indexb);
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end if;
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end process;
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end Behavioral;
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