133 lines
2.8 KiB
VHDL
133 lines
2.8 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity square_test is
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end square_test;
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architecture rtl of square_test is
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component square is
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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-- bus slave interface
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s_we : in std_logic;
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s_addr : in std_logic_vector(15 downto 0);
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s_din : in std_logic_vector(15 downto 0);
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-- bus master interface (DMA!!)
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m_busy : in std_logic;
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m_we : out std_logic;
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m_addr : out std_logic_vector(15 downto 0);
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m_dout : out std_logic_vector(15 downto 0)
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);
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end component;
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signal finished, clk, rst: std_logic := '0';
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signal s_we, m_busy, m_we: std_logic;
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signal s_addr, s_din, m_addr, m_dout: std_logic_vector(15 downto 0);
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constant period: integer := 7;
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constant half_time: time := 1280 ns * period;
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begin
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dut: square port map(clk => clk, rst => rst,
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s_we => s_we, s_addr => s_addr, s_din => s_din,
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m_busy => m_busy, m_we => m_we, m_addr => m_addr, m_dout => m_dout);
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-- tick tock
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process
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begin
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if finished = '0' then
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clk <= not clk;
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wait for 5 ns;
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else
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clk <= '0';
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wait;
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end if;
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end process;
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process
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begin
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rst <= '1';
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wait for 1 ns;
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assert(m_we='0') report "Fail rst" severity error;
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rst <= '0';
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m_busy <= '0';
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wait for 10 ns;
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s_we <= '1';
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s_addr <= x"0000"; -- period
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s_din <= std_logic_vector(to_unsigned(period, 16));
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wait for 10 ns;
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s_we <= '1';
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s_addr <= x"0002"; -- high
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s_din <= x"0042";
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wait for 10 ns;
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s_we <= '1';
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s_addr <= x"0004"; -- low
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s_din <= x"0037";
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wait for 10 ns;
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s_we <= '1';
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s_addr <= x"0006"; -- DMA address
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s_din <= x"babe";
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wait for 10 ns;
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s_we <= '1';
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s_addr <= x"0008"; -- enable
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s_din <= x"0001";
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wait for 20 ns;
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-- assert(m_addr = x"babe") report "Fail to write to mem addr" severity error;
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-- assert(m_we = '1') report "Fail to write to mem we" severity error;
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-- assert(m_dout = x"0037") report "Fail to write to mem dout" severity error;
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wait for 20 ns;
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-- assert(m_we = '0') report "Fail to stop m_we" severity error;
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wait for half_time;
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assert(m_dout = x"0037") report "Fail to write to mem dout" severity error;
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m_busy <= '1';
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wait for half_time;
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assert(m_we = '0') report "Blarg" severity error;
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assert(m_dout = x"0037") report "Fail to write to mem dout" severity error;
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m_busy <= '0';
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wait for 10 ns;
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assert(m_we = '1') report "Blarg" severity error;
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assert(m_dout = x"0042") report "Fail to write to mem dout" severity error;
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wait for 100 us;
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assert false report "Test done." severity note;
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finished <= '1';
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wait;
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end process;
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end rtl;
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