129 lines
3.0 KiB
VHDL
129 lines
3.0 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity pdmout_test is
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end pdmout_test;
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architecture rtl of pdmout_test is
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component pdmout is
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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-- hardware
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out_pin : out std_logic;
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-- bus interface
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we : in std_logic;
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addr : in std_logic_vector(15 downto 0);
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din : in std_logic_vector(15 downto 0)
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);
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end component;
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signal finished: std_logic := '0';
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signal clk: std_logic := '0';
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signal rst, bus_we, pdm_out: std_logic;
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signal bus_miso, bus_mosi, bus_addr: std_logic_vector(15 downto 0);
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begin
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dut: pdmout port map(clk => clk, rst => rst, out_pin => pdm_out,
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we => bus_we, addr => bus_addr,
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din => bus_mosi);
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process
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begin
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if finished = '0' then
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clk <= not clk;
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wait for 5 ns;
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else
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clk <= '0';
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wait;
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end if;
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end process;
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process
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begin
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rst <= '1';
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wait for 1 ns;
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assert(pdm_out='0') report "Fail rst" severity error;
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rst <= '0';
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wait for 10 ns;
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bus_addr <= x"0000";
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bus_mosi <= x"8000";
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bus_we <= '1';
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wait for 10 ns;
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assert(pdm_out='0') report "enabled didn't work?" severity error;
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bus_addr <= x"0002";
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bus_mosi <= x"0001";
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bus_we <= '1';
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wait for 10 ns;
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bus_addr <= x"0000";
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bus_we <= '0';
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wait for 20 ns;
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assert(pdm_out='1') report "output is wrong" severity error;
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wait for 10 ns;
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assert(pdm_out='0') report "output is wrong" severity error;
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wait for 10 ns;
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assert(pdm_out='1') report "output is wrong" severity error;
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wait for 10 ns;
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assert(pdm_out='0') report "output is wrong" severity error;
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wait for 10 ns;
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assert(pdm_out='1') report "output is wrong" severity error;
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wait for 10 ns;
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assert(pdm_out='0') report "output is wrong" severity error;
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bus_addr <= x"0000";
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bus_mosi <= x"0000";
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bus_we <= '1';
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wait for 10 ns;
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wait for 10 ns;
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assert(pdm_out='0') report "output is wrong" severity error;
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wait for 10 ns;
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assert(pdm_out='0') report "output is wrong" severity error;
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bus_addr <= x"0000";
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bus_mosi <= x"4000";
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bus_we <= '1';
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wait for 10 ns;
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wait for 10 ns;
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assert(pdm_out='0') report "output is wrong" severity error;
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wait for 10 ns;
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assert(pdm_out='0') report "output is wrong" severity error;
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wait for 10 ns;
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assert(pdm_out='1') report "output is wrong" severity error;
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wait for 10 ns;
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assert(pdm_out='0') report "output is wrong" severity error;
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wait for 10 ns;
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assert(pdm_out='0') report "output is wrong" severity error;
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wait for 10 ns;
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assert(pdm_out='0') report "output is wrong" severity error;
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wait for 10 ns;
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assert(pdm_out='1') report "output is wrong" severity error;
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wait for 10 ns;
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assert(pdm_out='0') report "output is wrong" severity error;
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assert false report "Test done." severity note;
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finished <= '1';
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wait;
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end process;
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end rtl;
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