242 lines
6.5 KiB
VHDL
242 lines
6.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity sysbus_test is
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end sysbus_test;
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architecture rtl of sysbus_test is
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component sysbus is
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port(
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clk: in std_logic;
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rst: in std_logic;
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-- master port 0
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m0_addr: in std_logic_vector(15 downto 0);
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m0_wdata: in std_logic_vector(15 downto 0);
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m0_rdata: out std_logic_vector(15 downto 0);
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m0_re: in std_logic;
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m0_we: in std_logic;
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m0_busy: out std_logic;
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-- master port 1
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m1_addr: in std_logic_vector(15 downto 0);
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m1_wdata: in std_logic_vector(15 downto 0);
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m1_rdata: out std_logic_vector(15 downto 0);
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m1_re: in std_logic;
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m1_we: in std_logic;
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m1_busy: out std_logic;
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-- actual bus
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bus_addr: out std_logic_vector(15 downto 0);
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bus_wdata: out std_logic_vector(15 downto 0);
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bus_rdata: in std_logic_vector(15 downto 0);
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bus_re: out std_logic;
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bus_we: out std_logic
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);
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end component;
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signal finished: std_logic := '0';
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signal clk, rst: std_logic := '0';
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signal m0_addr, m0_wdata, m0_rdata: std_logic_vector(15 downto 0);
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signal m0_re, m0_we, m0_busy: std_logic;
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signal m1_addr, m1_wdata, m1_rdata: std_logic_vector(15 downto 0);
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signal m1_re, m1_we, m1_busy: std_logic;
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signal bus_addr, bus_wdata, bus_rdata: std_logic_vector(15 downto 0);
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signal bus_re, bus_we : std_logic;
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signal bus_rdata_next: std_logic_vector(15 downto 0);
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begin
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dut: sysbus port map(clk => clk, rst => rst,
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m0_addr => m0_addr, m0_wdata => m0_wdata, m0_rdata => m0_rdata,
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m0_re => m0_re, m0_we => m0_we, m0_busy => m0_busy,
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m1_addr => m1_addr, m1_wdata => m1_wdata, m1_rdata => m1_rdata,
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m1_re => m1_re, m1_we => m1_we, m1_busy => m1_busy,
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bus_addr => bus_addr, bus_wdata => bus_wdata, bus_rdata => bus_rdata,
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bus_re => bus_re, bus_we => bus_we
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);
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-- clock
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process
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begin
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if finished = '0' then
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clk <= not clk;
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wait for 5 ns;
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else
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clk <= '0';
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wait;
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end if;
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end process;
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-- memory
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process(bus_re, bus_addr)
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begin
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bus_rdata_next <= x"0000";
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if bus_re = '1' then
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case bus_addr is
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when x"feed" =>
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bus_rdata_next <= x"babe";
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when x"dead" =>
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bus_rdata_next <= x"beef";
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when others =>
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end case;
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end if;
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end process;
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process(clk, rst)
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begin
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if rst = '1' then
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bus_rdata <= x"0000";
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elsif rising_edge(clk) then
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bus_rdata <= bus_rdata_next;
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end if;
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end process;
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process
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begin
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rst <= '1';
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m0_re <= '0';
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m0_we <= '0';
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m1_re <= '0';
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m1_we <= '0';
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wait for 1 ns;
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assert(m0_busy='0') report "Fail rst" severity error;
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assert(m1_busy='0') report "Fail rst" severity error;
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rst <= '0';
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wait for 10 ns;
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assert(m0_busy='0') report "Should still be idle" severity error;
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assert(m1_busy='0') report "Should still be idle" severity error;
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-- m0 write
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m0_addr <= x"feed";
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m0_wdata <= x"babe";
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m0_we <= '1';
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wait for 10 ns;
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assert(bus_addr=x"feed") report "Did not do write" severity error;
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assert(bus_wdata=x"babe") report "Did not do write" severity error;
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m0_we <= '0';
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-- read
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m0_re <= '1';
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wait for 10 ns;
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assert(m0_rdata=x"babe") report "Did not do read" severity error;
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assert(m1_busy='1') report "Did not do block m1 for m0 read" severity error;
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m0_re <= '0';
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wait for 10 ns;
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assert(m0_busy='0') report "m0 was not idle" severity error;
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assert(m1_busy='0') report "m1 was not idle" severity error;
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-- m1 write
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m1_addr <= x"dead";
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m1_wdata <= x"beef";
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m1_we <= '1';
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wait for 10 ns;
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assert(bus_addr=x"dead") report "Did not do write" severity error;
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assert(bus_wdata=x"beef") report "Did not do write" severity error;
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m1_we <= '0';
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-- read
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m1_re <= '1';
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wait for 10 ns;
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assert(m1_rdata=x"beef") report "Did not do read m1" severity error;
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assert(m0_busy='1') report "Did not do block m0 for m1 read" severity error;
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m1_re <= '0';
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wait for 10 ns;
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assert(m0_busy='0') report "m0 was not idle" severity error;
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assert(m1_busy='0') report "m1 was not idle" severity error;
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-- serious shit below
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-- concurent writes
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m0_addr <= x"feed";
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m0_wdata <= x"babe";
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m0_we <= '1';
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m1_addr <= x"dead";
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m1_wdata <= x"beef";
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m1_we <= '1';
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wait for 9 ns;
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assert(bus_addr=x"feed") report "Did not do write m0" severity error;
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assert(bus_wdata=x"babe") report "Did not do write m0" severity error;
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wait for 1 ns;
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assert(m1_busy='1') report "Did not do delay m1" severity error;
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m0_we <= '0';
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m1_we <= '0';
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wait for 9 ns;
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assert(bus_addr=x"dead") report "Did not do write m1" severity error;
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assert(bus_wdata=x"beef") report "Did not do write m1" severity error;
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wait for 1 ns;
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wait for 10 ns;
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assert(m0_busy='0') report "m0 was not idle" severity error;
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assert(m1_busy='0') report "m1 was not idle" severity error;
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-- concurrent reads (!!)
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m0_re <= '1';
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m1_re <= '1';
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wait for 10 ns;
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assert(m0_rdata=x"babe") report "Did not do read m0" severity error;
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assert(m1_busy='1') report "Did not do block m1 for m0 read" severity error;
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m0_re <= '0';
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wait for 20 ns;
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assert(m1_busy='0') report "m1 was not idle" severity error;
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assert(m1_rdata=x"beef") report "Did not do read m1" severity error;
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assert(m0_busy='1') report "Did not do block m0 for m1 read" severity error;
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m1_re <= '0';
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wait for 10 ns;
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assert(m0_busy='0') report "m0 was not idle" severity error;
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assert(m1_busy='0') report "m1 was not idle" severity error;
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-- concurrent read & write (OMG)
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m1_re <= '1';
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m0_we <= '1';
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wait for 10 ns;
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assert(m1_rdata=x"beef") report "Did not do read m1" severity error;
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assert(m0_busy='1') report "Did not do block m0 for m1 read" severity error;
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m1_re <= '0';
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wait for 10 ns;
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assert(bus_addr=x"feed") report "Did not do write m0" severity error;
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assert(bus_wdata=x"babe") report "Did not do write m0" severity error;
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m0_we <= '0';
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wait for 10 ns;
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assert(m0_busy='0') report "m0 was not idle" severity error;
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assert(m1_busy='0') report "m1 was not idle" severity error;
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assert false report "Test done." severity note;
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finished <= '1';
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wait;
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end process;
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end rtl;
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