74 lines
1.8 KiB
VHDL
74 lines
1.8 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 02/13/2021 12:09:57 AM
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-- Design Name:
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-- Module Name: top - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool Versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx leaf cells in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity top is
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Port ( clk : in STD_LOGIC;
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rst_n : in STD_LOGIC;
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led : out STD_LOGIC_VECTOR (7 downto 0);
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usb_rx: in std_logic;
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usb_tx: out std_logic
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);
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end top;
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architecture Behavioral of top is
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component hello is port(
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clk: in std_logic;
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rst: in std_logic;
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led: out std_logic_vector(7 downto 0);
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uart_rx: in std_logic;
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uart_tx: out std_logic
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);
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end component;
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component reset_conditioner is port(
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clk: in std_logic;
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rin: in std_logic;
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rout: out std_logic
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);
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end component;
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signal rst, rstraw: std_logic;
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begin
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rstraw <= not rst_n;
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reset: reset_conditioner port map(clk => clk, rin => rstraw, rout => rst);
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stuff: hello port map(clk => clk, rst => rst, led => led,
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uart_rx => usb_rx, uart_tx => usb_tx);
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end Behavioral;
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