40 lines
846 B
VHDL
40 lines
846 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Aligned IO only.
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-- Unaligned address bits are ignored.
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-- E.g. on a 16-bit bus, last address bit is ignored.
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entity rom is
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generic
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(
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addressWidth : in positive := 16;
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busWidth : in positive := 16
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);
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port
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(
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address : in unsigned(addressWidth - 1 downto 0);
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dataOut : out std_logic_vector(busWidth - 1 downto 0)
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);
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end rom;
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architecture Behavioral of rom is
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constant alignment : positive := busWidth / 8;
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type romtype is array(0 to 2) of std_logic_vector(15 downto 0);
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signal romdata: romtype := (
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x"0002",
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x"0004",
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x"0000"
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);
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begin
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process(address) is
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variable index: natural;
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begin
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index := to_integer(unsigned(address)) / alignment;
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dataOut <= romdata(index);
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end process;
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end Behavioral;
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