60 lines
1.1 KiB
VHDL
60 lines
1.1 KiB
VHDL
-- Simple OR gate design
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library IEEE;
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use IEEE.std_logic_1164.all;
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use std.textio.all;
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entity dff_test is
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end dff_test;
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architecture rtl of dff_test is
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component clock is
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port(clk: out std_logic);
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end component;
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component dff is
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port(
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clk: in std_logic;
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rst: in std_logic;
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d: in std_logic;
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q: out std_logic
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);
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end component;
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signal d, q, clk, rst: std_logic;
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begin
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heartbeat: clock port map(clk);
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dut: dff port map(clk, rst, d, q);
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process
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begin
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rst <= '1';
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wait for 10 ns;
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assert(q='0') report "Fail rst" severity error;
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rst <= '0';
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d <= '1';
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wait for 10 ns;
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assert(q='1') report "Fail d=1" severity error;
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rst <= '1';
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wait for 1 ns;
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assert(q='0') report "Async rst fail" severity error;
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rst <= '0';
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d <= '1';
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wait for 9 ns;
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d <= '0';
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wait for 1 ns;
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assert(q='1') report "Fail clk sync" severity error;
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wait for 9 ns;
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assert(q='0') report "Fail d=0" severity error;
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assert false report "Test done." severity note;
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wait;
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end process;
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end rtl;
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