148 lines
3.9 KiB
VHDL
148 lines
3.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity test_rom is
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generic
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(
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addressWidth : in positive := 16;
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busWidth : in positive := 16
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);
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port
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(
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address : in std_logic_vector(addressWidth - 1 downto 0);
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dataOut : out std_logic_vector(busWidth - 1 downto 0)
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);
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end test_rom;
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architecture Behavioral of test_rom is
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constant alignment: positive := busWidth / 8;
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--- type romtype is array(0 to 14) of std_logic_vector(15 downto 0);
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--- signal romdata: romtype := (
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---x"e180",
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---x"e200",
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---x"e301",
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---x"e4ff",
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---x"2210",
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---x"3223",
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---x"ed08",
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---x"ea00",
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---x"eb00",
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---x"3aa3",
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---x"fefe",
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---x"3bb3",
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---x"c0b4",
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---x"fef8",
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---x"ee08"
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---);
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type romtype is array(0 to 10) of std_logic_vector(15 downto 0);
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signal romdata: romtype := (
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x"0000", -- NOP
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x"e02a", -- SET r0, 42
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x"e125", -- SET r1, 37
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x"2010", -- STORE r0, [r1]
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x"1210", -- LOAD r2, [r1]
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x"3322", -- ADD r3, r2, r2
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x"2310", -- STORE r3, [r1]
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x"c020", -- CMP r0, r2
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x"de04", -- BEQ pc, 4
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x"0000", -- NOP
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x"ee00" -- SET pc, 0
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);
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begin
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process(address) is
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variable index: natural;
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begin
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index := to_integer(unsigned(address)) / alignment;
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dataOut <= romdata(index);
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end process;
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end Behavioral;
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---
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity cpu_test is
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end cpu_test;
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architecture rtl of cpu_test is
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component clock is port(clk: out std_logic);
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end component;
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component cpu is port(
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clk: in std_logic;
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rst: in std_logic;
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code_data: in std_logic_vector(15 downto 0);
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code_addr: out std_logic_vector(15 downto 0);
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mem_in: in std_logic_vector(15 downto 0);
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mem_out: out std_logic_vector(15 downto 0);
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mem_addr: out std_logic_vector(15 downto 0);
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mem_write: out std_logic
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);
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end component;
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component test_rom is port (
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address : in std_logic_vector(15 downto 0);
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dataOut : out std_logic_vector(15 downto 0)
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);
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end component;
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signal clk, rst, mem_write: std_logic;
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signal rom_data, rom_addr, mem_in, mem_out, mem_addr: std_logic_vector(15 downto 0);
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begin
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heartbeat: clock port map(clk);
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dut: cpu port map(clk, rst, rom_data, rom_addr, mem_in, mem_out, mem_addr, mem_write);
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rom: test_rom port map(rom_addr, rom_data);
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process
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begin
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rst <= '1';
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wait for 1 ns;
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assert(rom_addr=x"0000") report "Fail rst" severity error;
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rst <= '0';
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wait for 10 ns;
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assert(rom_addr=x"0002") report "Fail PC advance @00" severity error;
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wait for 20 ns;
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assert(rom_addr=x"0006") report "Fail PC @06" severity error;
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assert(mem_write='1') report "Fail set mem_write to 1" severity error;
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assert(mem_addr=x"0025") report "Fail set mem_addr to 0x25" severity error;
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assert(mem_out=x"002a") report "Fail set mem_out to 42" severity error;
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wait for 10 ns;
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assert(rom_addr=x"0008") report "Fail PC @08" severity error;
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assert(mem_write='0') report "Fail set mem_write to 0" severity error;
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assert(mem_addr=x"0025") report "Fail set mem_addr to 0x25" severity error;
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mem_in <= x"002a";
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wait for 20 ns;
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assert(rom_addr=x"000c") report "Fail PC @0c" severity error;
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assert(mem_write='1') report "Fail set mem_write to 1" severity error;
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assert(mem_addr=x"0025") report "Fail set mem_addr to 0x25" severity error;
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assert(mem_out=x"0054") report "Fail set mem_out to 84" severity error;
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wait for 30 ns;
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assert(rom_addr=x"0014") report "Fail to branch" severity error;
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wait for 10 ns;
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assert(rom_addr=x"0000") report "Fail to jump" severity error;
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assert false report "Test done." severity note;
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wait;
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end process;
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end rtl;
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