143 lines
1.9 KiB
VHDL
143 lines
1.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity boot_rom is
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generic
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(
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addressWidth : in positive := 16;
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busWidth : in positive := 16
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);
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port
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(
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clk: in std_logic;
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code_addr : in std_logic_vector(15 downto 0);
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code_out : out std_logic_vector(15 downto 0);
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data_addr : in std_logic_vector(15 downto 0);
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data_out : out std_logic_vector(15 downto 0)
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);
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end boot_rom;
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architecture Behavioral of boot_rom is
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constant alignment: positive := busWidth / 8;
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constant romsize: natural := 92;
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type romtype is array(0 to romsize - 1) of std_logic_vector(15 downto 0);
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signal romdata: romtype := (
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x"ec00",
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x"9c11",
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x"e28c",
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x"e302",
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x"3de3",
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x"5e22",
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x"5eee",
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x"e012",
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x"90c0",
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x"e102",
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x"1000",
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x"6201",
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x"e100",
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x"4021",
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x"5edd",
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x"e012",
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x"90c0",
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x"e101",
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x"1000",
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x"6201",
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x"e100",
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x"4021",
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x"5edd",
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x"2dcf",
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x"e404",
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x"4cc4",
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x"e11e",
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x"20c0",
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x"e002",
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x"3de0",
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x"5e11",
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x"e200",
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x"c200",
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x"fe02",
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x"e101",
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x"e000",
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x"c010",
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x"de06",
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x"10c0",
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x"c000",
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x"dee2",
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x"e010",
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x"90c0",
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x"12c0",
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x"2200",
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x"e204",
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x"3cc2",
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x"1ecf",
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x"2dcf",
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x"e402",
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x"4cc4",
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x"e00e",
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x"e102",
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x"3de1",
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x"5e00",
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x"e200",
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x"c200",
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x"fe02",
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x"e101",
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x"e000",
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x"c010",
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x"de04",
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x"c000",
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x"dee6",
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x"e010",
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x"90c0",
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x"1000",
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x"e202",
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x"3cc2",
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x"1ecf",
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x"2dcf",
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x"e404",
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x"4cc4",
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x"e001",
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x"e100",
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x"c100",
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x"de16",
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x"e160",
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x"e002",
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x"3de0",
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x"5e11",
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x"e12e",
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x"20c0",
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x"e202",
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x"3de2",
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x"5e11",
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x"c000",
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x"dee2",
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x"e000",
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x"e104",
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x"3cc1",
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x"1ecf"
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);
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begin
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process(clk) is
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variable code_index: natural;
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variable data_index: natural;
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begin
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if rising_edge(clk) then
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code_index := to_integer(unsigned(code_addr)) / alignment;
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if code_index < romsize then
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code_out <= romdata(code_index);
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else
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code_out <= x"0000";
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end if;
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data_index := to_integer(unsigned(data_addr)) / alignment;
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data_out <= romdata(data_index);
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end if;
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end process;
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end Behavioral;
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