49 lines
1.1 KiB
VHDL
49 lines
1.1 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use std.textio.all;
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entity vect_adder_test is
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end vect_adder_test;
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architecture rtl of vect_adder_test is
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component vect_adder is
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port(
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a, b : in std_logic_vector(15 downto 0);
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c_in : in std_logic;
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q : out std_logic_vector(15 downto 0);
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c_out : out std_logic
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);
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end component;
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signal a, b, q: std_logic_vector(15 downto 0);
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signal c_in, c_out: std_logic;
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begin
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dut: vect_adder port map(a, b, c_in, q, c_out);
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process
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begin
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a <= "0000000000000001";
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b <= "0000000000000001";
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c_in <= '0';
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wait for 1 ns;
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assert(q="0000000000000010") report "Fail 1+1" severity error;
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assert(c_out='0') report "Fail carry 1+1" severity error;
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a <= "1111111111111111";
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b <= "0000000000000001";
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c_in <= '0';
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wait for 1 ns;
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assert(q="0000000000000000") report "Fail 0xffff + 1" severity error;
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assert(c_out='1') report "Fail carry 0xffff + 1" severity error;
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-- end
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assert false report "Test done." severity note;
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wait;
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end process;
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end rtl;
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