106 lines
2.3 KiB
VHDL
106 lines
2.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity dsp_test is
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end dsp_test;
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architecture rtl of dsp_test is
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component clock is port(clk: out std_logic);
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end component;
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component dsp is
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port(
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clk: in std_logic;
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rst: in std_logic;
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led: out std_logic_vector(7 downto 0);
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uart0_rx: in std_logic;
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uart0_tx: out std_logic;
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pdmout0_pin: out std_logic;
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uart1_rx: in std_logic;
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uart1_tx: out std_logic
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);
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end component;
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signal finished, clk, rst: std_logic := '0';
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signal led: std_logic_vector(7 downto 0);
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signal uart0_rx: std_logic;
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signal uart0_tx: std_logic;
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signal uart1_rx: std_logic;
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signal uart1_tx: std_logic;
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signal pdmout0: std_logic;
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type str is array(integer range <>) of std_logic_vector(7 downto 0);
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signal prog: str(0 to 7) := (
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x"63", x"11", x"00", x"04", x"e0", x"00", x"5e", x"00");
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signal jump: str(0 to 2) := (
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x"6a", x"11", x"00");
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constant UART_PERIOD: time := 1000 ns;
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procedure uart_send(
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signal s: in str;
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signal o: out std_logic
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) is
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begin
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for i in s'range loop
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o <= '0'; -- start bit
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wait for UART_PERIOD;
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for j in 0 to 7 loop
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o <= s(i)(j);
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wait for UART_PERIOD;
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end loop;
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o <= '1'; -- stop bit
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wait for UART_PERIOD;
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end loop;
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end procedure;
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begin
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dut: dsp port map(clk => clk, rst => rst,
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led => led, uart0_rx => uart0_rx, uart0_tx => uart0_tx,
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uart1_rx => uart1_rx, uart1_tx => uart1_tx,
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pdmout0_pin => pdmout0);
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clk <= not clk after 5 ns when finished /= '1' else '0';
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process
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begin
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rst <= '1';
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uart0_rx <= '1';
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wait for 15 ns;
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assert(led=x"00") report "Fail rst" severity error;
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rst <= '0';
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wait for 20 us;
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uart_send(prog, uart0_rx);
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wait for 2 us;
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assert(led = x"f0") report "Fail prog" severity error;
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-- uart_send(jump, uart0_rx);
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-- wait for 2 us;
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-- assert(led = x"2a") report "Fail prog" severity error;
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-- wait for 200 us;
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-- uart_send(midi, uart1_rx);
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assert false report "Test done." severity note;
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finished <= '1';
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wait;
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end process;
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end rtl;
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