340 lines
9.7 KiB
VHDL
340 lines
9.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity dsp is
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port
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(
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clk: in std_logic;
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rst: in std_logic;
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led: out std_logic_vector(7 downto 0);
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uart0_rx: in std_logic;
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uart0_tx: out std_logic;
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pdmout0_pin: out std_logic;
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uart1_rx: in std_logic;
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uart1_tx: out std_logic
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);
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end dsp;
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architecture rtl of dsp is
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component cpu is port
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(
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clk: in std_logic;
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rst: in std_logic;
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code_data: in std_logic_vector(15 downto 0);
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code_addr: out std_logic_vector(15 downto 0);
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mem_in: in std_logic_vector(15 downto 0);
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mem_out: out std_logic_vector(15 downto 0);
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mem_addr: out std_logic_vector(15 downto 0);
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mem_write: out std_logic;
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mem_read: out std_logic;
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mem_busy: in std_logic
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);
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end component;
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component ram is
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generic
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(
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addressWidth : in positive := 16;
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busWidth : in positive := 16;
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size : in positive := 4096
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);
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port
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(
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clk : in std_logic;
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-- port A
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addra : in std_logic_vector(addressWidth - 1 downto 0);
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wea : in std_logic;
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dina : in std_logic_vector(busWidth - 1 downto 0);
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douta : out std_logic_vector(busWidth - 1 downto 0);
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-- port B (read only)
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addrb : in std_logic_vector(addressWidth - 1 downto 0);
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doutb : out std_logic_vector(busWidth - 1 downto 0)
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);
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end component;
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component boot_rom is port
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(
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clk: in std_logic;
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code_addr : in std_logic_vector(15 downto 0);
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code_out : out std_logic_vector(15 downto 0);
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data_addr : in std_logic_vector(15 downto 0);
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data_out : out std_logic_vector(15 downto 0)
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);
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end component;
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component uart is
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generic
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(
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baudrate : in natural := 1_000_000
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);
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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-- hardware
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rx_pin : in std_logic;
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tx_pin : out std_logic;
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-- bus interface
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we : in std_logic;
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re : in std_logic;
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addr : in std_logic_vector(15 downto 0);
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din : in std_logic_vector(15 downto 0);
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dout : out std_logic_vector(15 downto 0)
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);
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end component;
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component sysbus is
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port
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(
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clk: in std_logic;
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rst: in std_logic;
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-- master port 0
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m0_addr: in std_logic_vector(15 downto 0);
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m0_wdata: in std_logic_vector(15 downto 0);
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m0_rdata: out std_logic_vector(15 downto 0);
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m0_re: in std_logic;
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m0_we: in std_logic;
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m0_busy: out std_logic;
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-- master port 1
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m1_addr: in std_logic_vector(15 downto 0);
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m1_wdata: in std_logic_vector(15 downto 0);
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m1_rdata: out std_logic_vector(15 downto 0);
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m1_re: in std_logic;
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m1_we: in std_logic;
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m1_busy: out std_logic;
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-- actual bus
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bus_addr: out std_logic_vector(15 downto 0);
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bus_wdata: out std_logic_vector(15 downto 0);
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bus_rdata: in std_logic_vector(15 downto 0);
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bus_re: out std_logic;
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bus_we: out std_logic
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);
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end component;
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component pdmout is
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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-- hardware
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out_pin : out std_logic;
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-- bus interface
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we : in std_logic;
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addr : in std_logic_vector(15 downto 0);
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din : in std_logic_vector(15 downto 0)
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);
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end component;
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component square is
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port
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(
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clk : in std_logic;
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rst : in std_logic;
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-- bus slave interface
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s_we : in std_logic;
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s_addr : in std_logic_vector(15 downto 0);
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s_din : in std_logic_vector(15 downto 0);
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-- bus master interface (DMA!!)
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m_busy : in std_logic;
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m_we : out std_logic;
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m_addr : out std_logic_vector(15 downto 0);
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m_dout : out std_logic_vector(15 downto 0)
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);
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end component;
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signal mem_wea : std_logic;
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signal rom_code_addr, rom_code_out: std_logic_vector(15 downto 0);
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signal mem_dina, mem_douta, mem_addra: std_logic_vector(15 downto 0);
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signal mem_doutb, mem_addrb: std_logic_vector(15 downto 0);
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signal rom_data_addr, rom_data_out: std_logic_vector(15 downto 0);
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signal uart0_din, uart0_dout, uart0_addr: std_logic_vector(15 downto 0);
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signal uart0_we, uart0_re: std_logic;
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signal uart1_din, uart1_dout, uart1_addr: std_logic_vector(15 downto 0);
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signal uart1_we, uart1_re: std_logic;
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signal cpu_write, cpu_read, cpu_busy: std_logic;
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signal cpu_mosi, cpu_miso, cpu_addr: std_logic_vector(15 downto 0);
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signal square_write, square_busy: std_logic;
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signal square_mosi, square_addr: std_logic_vector(15 downto 0);
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signal square0_s_din, square0_s_addr: std_logic_vector(15 downto 0);
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signal square0_s_we : std_logic;
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signal pdmout0_din, pdmout0_addr: std_logic_vector(15 downto 0);
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signal pdmout0_we : std_logic;
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signal dbus_write, dbus_read: std_logic;
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signal dbus_mosi, dbus_miso, dbus_addr: std_logic_vector(15 downto 0);
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signal ibus_miso, ibus_addr: std_logic_vector(15 downto 0);
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signal led_r, led_next: std_logic_vector(7 downto 0);
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begin
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cpu0: cpu port map(clk => clk, rst => rst,
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code_data => ibus_miso, code_addr => ibus_addr,
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mem_in => cpu_miso, mem_out => cpu_mosi, mem_addr => cpu_addr,
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mem_write => cpu_write, mem_read => cpu_read, mem_busy => cpu_busy);
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rom: boot_rom port map(clk => clk, code_addr => rom_code_addr, code_out => rom_code_out,
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data_addr => rom_data_addr, data_out => rom_data_out);
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mem: ram port map(clk => clk,
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addra => mem_addra, wea => mem_wea, dina => mem_dina, douta => mem_douta,
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addrb => mem_addrb, doutb => mem_doutb);
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uart0: uart port map(clk => clk, rst => rst, rx_pin => uart0_rx, tx_pin => uart0_tx,
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addr => uart0_addr, din => uart0_din, dout => uart0_dout,
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re => uart0_re, we => uart0_we);
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uart1: uart generic map(baudrate => 31250)
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port map(clk => clk, rst => rst, rx_pin => uart1_rx, tx_pin => uart1_tx,
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addr => uart1_addr, din => uart1_din, dout => uart1_dout,
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re => uart1_re, we => uart1_we);
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square0: square port map(clk => clk, rst => rst,
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s_we => square0_s_we, s_addr => square0_s_addr, s_din => square0_s_din,
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m_busy => square_busy, m_we => square_write,
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m_addr => square_addr, m_dout => square_mosi);
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pdmout0: pdmout port map(clk => clk, rst => rst,
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out_pin => pdmout0_pin,
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we => pdmout0_we, addr => pdmout0_addr, din => pdmout0_din);
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main_bus: sysbus port map(clk => clk, rst => rst,
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m0_addr => cpu_addr, m0_wdata => cpu_mosi, m0_rdata => cpu_miso,
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m0_re => cpu_read, m0_we => cpu_write, m0_busy => cpu_busy,
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m1_addr => square_addr, m1_wdata => square_mosi, m1_rdata => open,
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m1_re => '0', m1_we => square_write, m1_busy => square_busy,
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bus_addr => dbus_addr, bus_wdata => dbus_mosi, bus_rdata => dbus_miso,
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bus_re => dbus_read, bus_we => dbus_write
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);
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-- system map
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-- 0x0000 - 0x0fff ROM
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-- 0x1000 - 0x1fff RAM
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-- 0xc000 - 0xc00f LED0
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-- 0xc010 - 0xc01f UART0 (1 Mbaud)
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-- 0xc020 - 0xc02f PDMOUT0
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-- 0xc030 - 0xc03f SQUARE0
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-- 0xc040 - 0xc04f UART1 (31250 baud)
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led <= led_r;
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-- IBUS interconnect
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mem_addrb <= x"0" & ibus_addr(11 downto 0);
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rom_code_addr <= x"0" & ibus_addr(11 downto 0);
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process(ibus_addr, rom_code_out, mem_doutb)
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begin
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case ibus_addr(15 downto 12) is
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when x"0" =>
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ibus_miso <= rom_code_out;
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when x"1" =>
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ibus_miso <= mem_doutb;
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when others =>
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ibus_miso <= x"0000";
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end case;
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end process;
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-- LED
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process(clk, rst)
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begin
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if rising_edge(clk) then
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led_r <= led_next;
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end if;
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if rst = '1' then
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led_r <= x"00";
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end if;
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end process;
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-- DBUS interconnect
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mem_addra <= x"0" & dbus_addr(11 downto 0);
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rom_data_addr <= x"0" & dbus_addr(11 downto 0);
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uart0_addr <= x"000" & dbus_addr(3 downto 0);
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uart1_addr <= x"000" & dbus_addr(3 downto 0);
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pdmout0_addr <= x"000" & dbus_addr(3 downto 0);
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square0_s_addr <= x"000" & dbus_addr(3 downto 0);
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process(dbus_addr, dbus_mosi, dbus_write, mem_douta, rst, rom_data_out, led_r, dbus_read, uart0_dout, uart1_dout)
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begin
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dbus_miso <= x"0000";
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mem_dina <= dbus_mosi;
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mem_wea <= '0';
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led_next <= led_r;
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uart0_din <= dbus_mosi;
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uart0_we <= '0';
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uart0_re <= '0';
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uart1_din <= dbus_mosi;
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uart1_we <= '0';
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uart1_re <= '0';
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pdmout0_we <= '0';
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pdmout0_din <= dbus_mosi;
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square0_s_we <= '0';
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square0_s_din <= dbus_mosi;
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case dbus_addr(15 downto 12) is
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when x"0" =>
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dbus_miso <= rom_data_out;
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when x"1" =>
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dbus_miso <= mem_douta;
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mem_wea <= dbus_write;
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when x"c" =>
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case dbus_addr(7 downto 4) is
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when x"0" => -- LED
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if dbus_write = '1' then
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led_next <= dbus_mosi(7 downto 0);
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end if;
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when x"1" => -- UART0
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dbus_miso <= uart0_dout;
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uart0_we <= dbus_write;
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uart0_re <= dbus_read;
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when x"2" => -- PDMOUT0
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pdmout0_we <= dbus_write;
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when x"3" => -- SQUARE0
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square0_s_we <= dbus_write;
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when x"4" => -- UART1
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dbus_miso <= uart1_dout;
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uart1_we <= dbus_write;
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uart1_re <= dbus_read;
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when others =>
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end case;
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when others =>
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end case;
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end process;
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end rtl;
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