133 lines
3.9 KiB
VHDL
133 lines
3.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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entity cpu_test is
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end cpu_test;
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architecture rtl of cpu_test is
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component cpu is port(
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clk: in std_logic;
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rst: in std_logic;
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code_data: in std_logic_vector(15 downto 0);
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code_addr: out std_logic_vector(15 downto 0);
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mem_in: in std_logic_vector(15 downto 0);
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mem_out: out std_logic_vector(15 downto 0);
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mem_addr: out std_logic_vector(15 downto 0);
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mem_write: out std_logic;
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mem_read: out std_logic;
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mem_busy: in std_logic
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);
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end component;
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type romtype is array(0 to 11) of std_logic_vector(15 downto 0);
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signal romdata: romtype := (
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x"0000", -- NOP
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x"e02a", -- SET r0, 42
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x"e125", -- SET r1, 37
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x"2010", -- STORE r0, [r1]
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x"1210", -- LOAD r2, [r1]
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x"3322", -- ADD r3, r2, r2
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x"2310", -- STORE r3, [r1]
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x"c020", -- CMP r0, r2
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x"de01", -- BEQ pc, 2
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x"0000", -- NOP
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x"ee00", -- SET pc, 0
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x"0000"
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);
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signal finished, clk, rst: std_logic := '0';
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signal mem_write, mem_read, mem_busy: std_logic;
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signal rom_data, rom_addr, mem_in, mem_out, mem_addr: std_logic_vector(15 downto 0);
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begin
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dut: cpu port map(clk => clk, rst => rst,
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code_data => rom_data, code_addr => rom_addr,
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mem_in => mem_in, mem_out => mem_out, mem_addr => mem_addr,
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mem_write => mem_write, mem_read => mem_read, mem_busy => mem_busy);
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-- clock
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process
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begin
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if finished = '0' then
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clk <= not clk;
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wait for 5 ns;
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else
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clk <= '0';
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wait;
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end if;
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end process;
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-- rom
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process(clk) is
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variable code_index: natural;
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variable data_index: natural;
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constant alignment: positive := 16 / 8;
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begin
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if rising_edge(clk) then
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code_index := to_integer(unsigned(rom_addr)) / alignment;
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rom_data <= romdata(code_index);
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end if;
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end process;
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process(rom_addr)
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constant alignment: positive := 16 / 8;
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variable index: natural;
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begin
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end process;
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process
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begin
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rst <= '1';
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wait for 1 ns;
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assert(rom_addr=x"0000") report "Fail rst" severity error;
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rst <= '0';
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wait for 10 ns;
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assert(rom_addr=x"0002") report "Fail PC advance @00" severity error;
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wait for 30 ns;
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assert(rom_addr=x"0008") report "Fail PC @06" severity error;
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assert(mem_write='1') report "Fail set mem_write to 1" severity error;
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assert(mem_addr=x"0025") report "Fail set mem_addr to 0x25" severity error;
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assert(mem_out=x"002a") report "Fail set mem_out to 42" severity error;
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mem_busy <= '1';
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wait for 10 ns;
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assert(rom_addr=x"0008") report "Fail hold PC @08" severity error;
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assert(mem_read='0') report "Fail to wait until mem_busy is low" severity error;
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mem_busy <= '0';
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wait for 10 ns;
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assert(rom_addr=x"000a") report "Fail PC @08" severity error;
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assert(mem_write='0') report "Fail set mem_write to 0" severity error;
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assert(mem_read='1') report "Fail set mem_read to 1" severity error;
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assert(mem_addr=x"0025") report "Fail set mem_addr to 0x25" severity error;
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mem_in <= x"002a";
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wait for 30 ns;
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assert(rom_addr=x"000e") report "Fail PC @0c" severity error;
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assert(mem_write='1') report "Fail set mem_write to 1" severity error;
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assert(mem_addr=x"0025") report "Fail set mem_addr to 0x25" severity error;
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assert(mem_out=x"0054") report "Fail set mem_out to 84" severity error;
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wait for 40 ns;
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assert(rom_addr=x"0016") report "Fail to branch" severity error;
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wait for 10 ns;
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assert(rom_addr=x"0000") report "Fail to jump" severity error;
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assert false report "Test done." severity note;
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finished <= '1';
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wait;
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end process;
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end rtl;
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